标题: | 应用于物联网之28奈米4kb 1写2读次临界施密特触发器先进先出随机静态存取记忆体设计 28nm 4kb 1W2R Sub-threshold Schmitt Trigger SRAM First-In-First-Out (FIFO) for IoT Applications |
作者: | 曾焕然 庄景德 黄威 Tseng, Huan-Jan Chuang, Ching-Te Hwang, Wei 电子研究所 |
关键字: | 先进先出记忆体;静态随机存取记忆体;施密特触发器;First-In-First-Out (FIFO);SRAM;Schmitt Trigger |
公开日期: | 2017 |
摘要: | 在许多系统晶片上,先进先出记忆体很常使用在资料暂存和流程控制。同时,多端静态随机存取记忆体也大量应用在可携式电子产品中的处理器。在本论文中,首先,提出一多端操作在次临界施密特触发器12.5T静态随机存取记忆体储存单元结合十自点资料察觉写入字元线,其用于位元交错架构。为了达到稳定的低压操作,此12.5T单元增加了保存静态杂讯边界以及消除写入半选择扰动。第二,此电路同时采用一个可调式读取操作时间追溯电路与负电压字元线电路,以达到PVT变动容忍的读取操作及增强写入能力。第三,提出了涟波字元线架构利用涟波缓冲器将字元线分割成数个区块降低导线延迟。最后,以联电28奈米高介电质金属闸极技术来实作一个4kb多端施密特触发器12.5T静态随机存取记忆体为基础及运用上述节能技术的先进先出记忆体。比起之前的先进先出记忆体,它能同时进行一个写入两个读取的执行,在更好的保存静态杂讯边界下,提高了两倍输出量,是适合应用在物联网的先进先出记忆体。 FIFO memory is commonly used for data buffers and flow control in many SoC applications. Simultaneously, multi-port SRAM is widely used in in many processing units of portable electronic products. In this thesis, first, we propose a multi-port sub-threshold Schmitt trigger 12.5T SRAM bit-cell with cross-point data-aware Write word-line for bit-interleaving structure. The ST12.5T cell not only increases hold static noise margin but also eliminates write half-select disturbance for robust sub-threshold operation. Secondly, an adaptive read operation timing tracing circuit and negative bit-line circuit are employed in the design for PVT variation-tolerant read operation and write ability enhancement. Thirdly, the proposed ripple bit-line structure divides the bit-line into several segments. Therefore, the wire delay can be reduced apparently. Finally, a 4kb FIFO memory in UMC 28nm HKMG technology with the proposed multi-port Schmitt trigger 12.5T SRAM bit-cell is implemented. It can execute one write and two read operation simultaneously. Under the condition with better HSNM comparing to previous FIFO memories, this design has double output which is suitable for IoT applications. |
URI: | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070450227 http://hdl.handle.net/11536/142525 |
显示于类别: | Thesis |