應用於物聯網之28奈米4kb 1寫2讀次臨界施密特觸發器先進先出隨機靜態存取記憶體設計

Abstract

在許多系統晶片上，先進先出記憶體很常使用在資料暫存和流程控制。同時，多端靜態隨機存取記憶體也大量應用在可攜式電子產品中的處理器。在本論文中，首先，提出一多端操作在次臨界施密特觸發器12.5T靜態隨機存取記憶體儲存單元結合十自點資料察覺寫入字元線，其用於位元交錯架構。為了達到穩定的低壓操作，此12.5T單元增加了保存靜態雜訊邊界以及消除寫入半選擇擾動。第二，此電路同時採用一個可調式讀取操作時間追溯電路與負電壓字元線電路，以達到PVT變動容忍的讀取操作及增強寫入能力。第三，提出了漣波字元線架構利用漣波緩衝器將字元線分割成數個區塊降低導線延遲。最後，以聯電28奈米高介電質金屬閘極技術來實作一個4kb多端施密特觸發器12.5T靜態隨機存取記憶體為基礎及運用上述節能技術的先進先出記憶體。比起之前的先進先出記憶體，它能同時進行一個寫入兩個讀取的執行，在更好的保存靜態雜訊邊界下，提高了兩倍輸出量，是適合應用在物聯網的先進先出記憶體。

FIFO memory is commonly used for data buffers and flow control in many SoC applications. Simultaneously, multi-port SRAM is widely used in in many processing units of portable electronic products. In this thesis, first, we propose a multi-port sub-threshold Schmitt trigger 12.5T SRAM bit-cell with cross-point data-aware Write word-line for bit-interleaving structure. The ST12.5T cell not only increases hold static noise margin but also eliminates write half-select disturbance for robust sub-threshold operation. Secondly, an adaptive read operation timing tracing circuit and negative bit-line circuit are employed in the design for PVT variation-tolerant read operation and write ability enhancement. Thirdly, the proposed ripple bit-line structure divides the bit-line into several segments. Therefore, the wire delay can be reduced apparently. Finally, a 4kb FIFO memory in UMC 28nm HKMG technology with the proposed multi-port Schmitt trigger 12.5T SRAM bit-cell is implemented. It can execute one write and two read operation simultaneously. Under the condition with better HSNM comparing to previous FIFO memories, this design has double output which is suitable for IoT applications.