低功率時間共享多線程暫存器

Abstract

本論文提出一個低功率多線程的暫存器設計。此暫存器被切成數個小區塊，並且應用了時間共享的機制去增加它的效能。為了節省功率的消耗，提出了免充電位元線和切割小位元線的方法。而且，此暫存器可以正確操作在大範圍的工作電壓下，可依效能和功率的要求去做電壓上的調整。此二線程的暫存器包括了四個存╱取埠，每個線程有64x64個位元大小，並以TSMC 90nm CMOS的製程技術做設計，實現在426 x 219 μm2的面積上。它的工作電壓範圍在0.5伏到1.0伏。當時脈為50MHz，它工作所消耗的功率在215.51微瓦 和 197.77微瓦之間。

A low-power multithreaded register file architecture is proposed. Banking architecture and timing sharing access scheme are adopted to reduce the register file area and increase its performance. Floating bitline scheme and divide bitline is also presented to reduce its active power. Furthermore, the register file architecture can be operated at a wide voltage range, and processors would have more strategies to adjust their power/performance. A dual-thread 4W/4R 64x64-bit register file which occupies 426 x 219 μm2 silicon area is implemented in UMC 90nm CMOS technology. Its operating voltage range is between 0.5v and 1.0v. Its active power is around 215.28μW to 197.87μW when operating frequency is 50MHz at 0.5v.