1. 目前位置：

瀏覽 的方式： 作者 Wang, Pei-Yu

跳到： 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
或是輸入前幾個字：  
顯示 1 到 11 筆資料，總共 11 筆
公開日期標題作者
一月-2016Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET StructureWang, Pei-Yu; Tsui, Bing-Yue; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2016Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET StructureWang, Pei-Yu; Tsui, Bing-Yue; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2014Enhancing the Performance of Germanium Channel nMOSFET Using Phosphorus Dopant SegregationChen, Che-Wei; Tzeng, Ju-Yuan; Chung, Cheng-Ting; Chien, Hung-Pin; Chien, Chao-Hsin; Luo, Guang-Li; Wang, Pei-Yu; Tsui, Bing-Yue; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015Evaluation of Electrical Performance of Various Tunnel TFETsHuang, Chi; Hung, Tao-Yi; Wang, Pei-Yu; Tsui, Bing-Yue; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2015Experimental Demonstration of p-Channel Germanium Epitaxial Tunnel Layer (ETL) Tunnel FET With High Tunneling Current and High ON/OFF RatioWang, Pei-Yu; Tsui, Bing-Yue; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
四月-2016Investigation Into Gate-to-Source Capacitance Induced by Highly Efficient Band-to-Band Tunneling in p-Channel Ge Epitaxial Tunnel Layer Tunnel FETWang, Pei-Yu; Tsui, Bing-Yue; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2010Multi-gate non-volatile memories with nanowires as charge storage materialTsui, Bing-Yue; Wang, Pei-Yu; Chen, Ting-Yeh; Cheng, Jung-Chien; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2015A Novel Approach Using Discrete Grain-Boundary Traps to Study the Variability of 3-D Vertical-Gate NAND Flash Memory CellsWang, Pei-Yu; Tsui, Bing-Yue; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014Simulation of Grain-Boundary Traps Effect for 3D Vertical Gate NAND Flash Memory Cell : From Structure Geometry to Trap DescriptionWang, Pei-Yu; Tsui, Bing-Yue; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2013SixGe1-x Epitaxial Tunnel Layer Structure for P-Channel Tunnel FET ImprovementWang, Pei-Yu; Tsui, Bing-Yue; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015磊晶穿隧層穿隧電晶體之研究王培宇; 崔秉鉞; Wang, Pei-Yu; Tsui, Bing-Yue; 電子工程學系 電子研究所
顯示 1 到 11 筆資料，總共 11 筆