瀏覽 的方式: 作者 Wu, Meng-Chen

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2011Design-for-Debug Layout Adjustment for FIB Probing and Circuit EditingChen, Kuo-An; Chang, Tsung-Wei; Wu, Meng-Chen; Chao, Mango C. -T.; Jou, Jing-Yang; Chen, Sonair; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Mixed Non-Rectangular Block Packing for Non-Manhattan Layout ArchitecturesWu, Meng-Chen; Chen, Hung-Ming; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Multiple-Fault Diagnosis Using Faulty-Region IdentificationTasi, Meng-Jai; Chao, Mango C. -T.; Jou, Jing-Yang; Wu, Meng-Chen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006Performance constraints aware voltage islands generation in SoC floorplan designLu, Ming-Ching; Wu, Meng-Chen; Chen, Hung-Ming; Jiang, Hui-Ru; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2009Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC FloorplanningWu, Meng-Chen; Lu, Ming-Ching; Chen, Hung-Ming; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2010在實體設計階段改善設計品質/診斷能力之方法吳孟臻; Wu, Meng-Chen; 周景揚; Jou, Jing-Yang; 電子研究所