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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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🏛️國立陽明交通大學機構典藏

Access type: Metadata onlyAuthor: search.filters.author.Hsu, KC

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Now showing 1 - 7 of 7
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    On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process
    (2002)
    Ker, MD
    ;
    Hsu, KC
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the, transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of SCR can be greatly improved by applying the substrate-triggered method. The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25-mum CMOS process. The substrate-triggered SCR device with a smaller layout area of only 40mumx20mum can sustain the HBM ESD stress of higher than 7kV.
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    ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
    (2002)
    Ker, MD
    ;
    Chuang, CH
    ;
    Hsu, KC
    ;
    Lo, WY
    ;
    電子工程學系及電子研究所
    A substrate-triggered technique is proposed to improve ESD Protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5V/3.3V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-mum salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased similar to 65% by this substrate-triggered design.
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    Complementary substrate-triggered SCR devices for on-chip ESD protection circuits
    (2002)
    Ker, MD
    ;
    Hsu, KC
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    The turn-on mechanism of SCR device is essentially a current triggering event. While a current is applied to the base or substrate of a SCR device, it can be quickly triggered on into its latching state. In this paper, the complementary substrate-triggered SCR devices which are combined with the substrate-triggered technique and SCR devices, are first reported in the literature for using in the on-chip ESD. protection circuits. A complementary style on the substrate-triggered SCR devices is designed to discharge both of the positive and negative ESD stresses on the pad. The total holding voltage of the substrate-triggered SCR device can be increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices for the I/O pad and power pad have been successfully verified in a 0.25-mum STI CMOS process with the HBM (MM) ESD level of >8kV (650V) in a small layout area.
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    Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-mu m CMOS integrated circuits
    (2004)
    Ker, MD
    ;
    Hsu, KC
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-mum CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and CDM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-mum CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.
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    Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices
    (2005)
    Ker, MD
    ;
    Chen, JH
    ;
    Hsu, KC
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    A novel self-substrate-triggered (SST) technique is proposed to solve the non-uniform turn-on issue of the multi-finger GGNMOS for ESD protection. The first turned-on center finger is used to trigger on all fingers in the GGNMOS structure with self-substrate-triggered technique. So, the turn-on uniformity and ESD robustness of GGNMOS can be greatly improved by the new proposed self-substrate-triggered technique.
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    Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
    (2005)
    Ker, MD
    ;
    Chen, WY
    ;
    Hsu, KC
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    A new power-rail ESD clamp circuit in a 130-nm 1-V/2.5-V CMOS process for application in 3.3-V mixed-voltage I/O interface is proposed. The devices used in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage NMOS/PMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V 1/0 interface applications. A special ESD detection circuit realized with the low-voltage devices is designed to improve ESD robustness of the stacked NMOS by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.
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    Miniaturized 3-dimensional transformer design
    (2005)
    Chen, WZ
    ;
    Hsu, KC
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    3-dimentional fully-symmetric transformers are proposed and realized in a standard CMOS technology. In contrast to their planar counterparts, the self resonant frequency (f(SR)) of the proposed architecture is improved by 26 % to 53 %, while the chip area is reduced by 40 % to 70 %. The coupling coefficient (K) can be up to 0.77 at 8 GHz in a two turn two layer architecture. Distributed capacitance model (DCM) of the 3-D transformer is also proposed f(SR) evaulation.