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Halbleitervorrichtung und Verfahren zur Herstellung derselben
(2018-06-21)
CHANG EDWARD YI
;
LIU SHIH-CHIEN
;
HUANG CHUNG-KAI
;
WU CHIA-HSUN
;
HAN PING-CHENG
A semiconductor device includes a substrate, a channel layer, a barrier layer, a recess, a charge trapping layer, a ferroelectric material layer, a gate, a source and a drain. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The barrier layer has a recess, and a portion of the barrier layer under the recess has a thickness. The source and the drain are disposed on the barrier layer. The charge trapping layer covers the bottom of the recess. The ferroelectric material is disposed on the charge trapping layer. The gate is disposed on the ferroelectric material.
Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs Using Active-Region Bumps-Induced Piezoelectric Effect
(2014-07-01)
Tsai, Szu-Ping
;
Hsu, Heng-Tung
;
Chiang, Che-Yang
;
Tu, Yung-Yi
;
Chang, Chia-Hua
We experimentally investigated the impact of different bump patterns on the output electrical characteristics of flip-chip (FC) bonded AlGaN/GaN high-electron mobility transistors in this letter. The bump patterns were designed and intended to provide different levels of tensile stress due to the mismatch in the coefficient of thermal expansion between the materials. After FC packaging, a maximum increase of 4.3% in saturation current was achieved compared with the bare die when proper arrangement of the bumps in active region was designed. In other words, a 17% improvement has been observed on the optimized bump pattern over the conventional bump pattern. To the best of our knowledge, this is the first letter that investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging.
Reliability improvement in GaN HEMT power device using a field plate approach
(2017-07-01)
Wu, Wen-Hao
;
Lin, Yueh-Chin
;
Chin, Ping-Chieh
;
Hsu, Chia-Chieh
;
Lee, Jin-Hwa
This study investigates the effect of implementing a field plate on a GaN high-electron-mobility transistor (HEMT) to improve power device reliability. The results indicate that the field plate structure reduces the peak electrical field and interface traps in the device, resulting in higher breakdown voltage, lower leakage current, smaller current collapse, and better threshold voltage control. Furthermore, after high voltage stress, steady dynamic on-resistance and gate capacitance degradation improvement were observed for the device with the field plate. This demonstrates that GaN device reliability can be improved by using the field plate approach. (C) 2017 Elsevier Ltd. All rights reserved.
High-Performance Normally-OFF GaN MIS-HEMTs Using Hybrid Ferroelectric Charge Trap Gate Stack (FEG-HEMT) for Power Device Applications
(2018-07-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
;
Liu, Shih-Chien
;
Hsieh, Ting-En
;
Lumbantoruan, Franky Juanda
A GaN metal-insulator-semiconductor-high electron mobility transistor (HEMT) using hybrid ferroelectric charge trap gate stack (FEG-HEMT) is demonstrated for normally-OFF operation. The ferroelectric (FE) polarization increases the number of trapped charges in the HfON charge trapping layer, leading to high positive threshold voltage (V-th) shift for the normally-OFF device. Besides, under the positive bias temperature instability (PBTI) test, the internal electric field induced by FE polarization causes smoother slope of the conduction band in FE gate stack, resulting in better V-th stability. With the proposed hybrid FE charge trap gate stack, the device exhibits a high V-th of +2.71 V at I-DS = 1 mu A/mm, a high maximum current density of 820 mA/mm and low on-resistance (R-ON) of 11.1 Omega . mm. The FE device also shows good V-th-temperature stability compared to the non-FE device results. Besides, a high current device with 40 A is also fabricated in this letter to demonstrate the feasibility of the proposed FEG-HEMT device for high power device application.
AlGaN/GaN MIS-HEMTs With High Quality ALD-Al2O3 Gate Dielectric Using Water and Remote Oxygen Plasma As Oxidants
(2018-12-01)
Wang, Huan-Chung
;
Hsieh, Ting-En
;
Lin, Yueh-Chin
;
Luc, Quang Ho
;
Liu, Shih-Chien
We demonstrate the electrical performances of AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistors (MIS-HEMTs) with high quality Al2O3 gate dielectric deposited by plasma enhanced atomic layer deposition using both H2O and remote O-2 plasma as oxygen sources. Excellent gate-dielectric/GaN interface and Al2O3 film quality were obtained, resulting in a very small threshold voltage hysteresis and a low interface trap density. The MIS-HEMT device exhibited high on/off current ratio of similar to 10(10), steep subthreshold slope, small gate leakage current, low dynamic on-resistance degradation, and effectively current collapse suppression. These results indicate that incorporating remote O-2 plasma in the ALD-Al2O3 deposition process is an effective and simple way to provide high quality gate dielectric for the GaN MIS-HEMTs production.
AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications (vol 37, pg 1395, 2016)
(2017-01)
Lin, Yen-Ku
;
Noda, Shuichi
;
Lo, Hsiao-Chieh
;
Liu, Shih-Chien
;
Wu, Chia-Hsun
AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications (vol 37, pg 1395, 2016)
(2017-01)
Lin, Yen-Ku
;
Noda, Shuichi
;
Lo, Hsiao-Chieh
;
Liu, Shih-Chien
;
Wu, Chia-Hsun
AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications
(2016-11)
Lin, Yen-Ku
;
Noda, Shuichi
;
Lo, Hsiao-Chieh
;
Liu, Shih-Chien
;
Wu, Chia-Hsun
The electrical performances of gate-recessed AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated using the damage-free neutral beam etching (NBE) method are demonstrated. The NBE method could eliminate the plasma-induced defects generated by irradiating ultraviolet/VUV photons in the conventional inductively coupled plasma reactive ion etching method. The AlGaN/GaN HEMT device fabricated using the new gate recess process exhibited superior electrical performances, including a maximum drain current density (I-DS,I-max) of 1.54 A/mm, low 1/f noise, a current-gain cutoff frequency (f(T)) of 153 GHz, a maximum frequency of oscillation (f(MAX)) of 167 GHz, and a minimum noise figure (NFmin) of 3.28 dB with an associated gain (G(AS)) of 5.06 dB at 54 GHz. Such superior characteristics confirm the inherent advantages of adopting the damage-free NBE process in fabricating GaN devices for millimeter-wave applications.
Effective surface treatment for GaN metal-insulator-semiconductor high-electron-mobility transistors using HF plus N-2 plasma prior to SiN passivation
(2016-01)
Liu, Shih-Chien
;
Trinh, Hai-Dang
;
Dai, Gu-Ming
;
Huang, Chung-Kai
;
Dee, Chang-Fu
An effective surface cleaning technique is demonstrated for the GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) passivation process. In this study, dilute HF solution and in situ N-2 plasma treatments were adopted to remove the native oxide and recover the nitrogen-vacancy defects at the GaN surface before device passivation. To investigate the correlation between the properties of the SiN/GaN interface and the device performance, the GaN MIS-HEMTs were characterized using current-voltage (I-V) measurement, capacitance-voltage (C-V) measurement, and X-ray photoelectron spectroscopy (XPS) analysis. With the application of this surface treatment technique, the device exhibits improved I-V characteristics with low leakage current, low dynamic ON-resistance, and good C-V response with a steep slope. Overall, the results reveal that the oxide-related bonds and nitrogen-vacancy defects at the SiN/GaN interface are the root cause of the GaN MIS-HEMTs performance degradation. (C) 2016 The Japan Society of Applied Physics
Electrical Analysis and PBTI Reliability of In0.53Ga0.47As MOSFETs With AlN Passivation Layer and NH3 Postremote Plasma Treatment
(2016-09)
Chang, Po-Chun
;
Luc, Quang-Ho
;
Lin, Yueh-Chin
;
Liu, Shih-Chien
;
Lin, Yen-Ku
We report a notable improvement in performance, electron transport, and reliability of HfO2/In0.53Ga0.47As nMOSFETs using a plasma-enhanced atomic layer deposition AlN interfacial passivation layer (IPL) and NH3 postremote plasma treatment (PRPT). The interface state density Dit decreased by approximately one order of magnitude from 6.1x10(12) to 4x10(11) cm(-2)eV(-1), and the border trap density N-bt also declined ten times from 2.8x10(19) to 2.7x10(18) cm(-3), resulting in the reduction of the accumulation frequency dispersion and eliminate the inversion hump in C-V characteristics, and thus improves the device performances. Furthermore, positive bias temperature instability stress indicates that the sample with the AlN IPL and NH3 PRPT is more reliable than the sample without any IPL and plasma treatment. During PBT stress, a smaller threshold voltage shift and less transconductance degradation were observed for the sample with the AlN IPL and NH3 PRPT. In addition, the maximum overdrive voltage for a ten-year operating lifetime increased from 0.19 to 0.41 V.

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