<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css">

學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Access type: Metadata onlySubject: search.filters.subject.CVD

Search Results

Now showing 1 - 10 of 11
  • Thumbnail Image
    Item type:Item,
    Layer-Dependent and In-Plane Anisotropic Properties of Low-Temperature Synthesized Few-Layer PdSe2 Single Crystals
    (2020-04-28)
    Lu, Li-Syuan
    ;
    Chen, Guan-Hao
    ;
    Cheng, Hui-Yu
    ;
    Chuu, Chih-Piao
    ;
    Lu, Kuan-Cheng
    Palladium diselenide (PdSe2), a peculiar noble metal dichalcogenide, has emerged as a new two-dimensional material with high predicted carrier mobility and a widely tunable band gap for device applications. The inherent in-plane anisotropy endowed by the pentagonal structure further renders PdSe2 promising for novel electronic, photonic, and thermoelectric applications. However, the direct synthesis of few-layer PdSe2 is still challenging and rarely reported. Here, we demonstrate that few-layer, single-crystal PdSe2 flakes can be synthesized at a relatively low growth temperature (300 degrees C) on sapphire substrates using low-pressure chemical vapor deposition (CVD). The well-defined rectangular domain shape and precisely determined layer number of the CVD-grown PdSe2 enable us to investigate their layer-dependent and in-plane anisotropic properties. The experimentally determined layer-dependent band gap shrinkage combined with first-principle calculations suggest that the interlayer interaction is weaker in few-layer PdSe2 in comparison with that in bulk crystals. Field-effect transistors based on the CVD-grown PdSe2 also show performances comparable to those based on exfoliated samples. The low-temperature synthesis method reported here provides a feasible approach to fabricate high-quality few-layer PdSe2 for device applications.
  • Thumbnail Image
    Item type:Item,
    Low-temperature CVD growth of carbon nanotubes for field emission application
    (2007-03-01)
    Chen, Kuang-Chung
    ;
    Chen, Chia-Fu
    ;
    Lee, Jen-Hao
    ;
    Wu, Tai-Lin
    ;
    Hwang, Chian-Liang
    For field emission application, carbon nanotube emitters were synthesized on catalyst-mixed thick-film electrode lower than 500 degrees C by chemical vapor deposition (CVD) method. Mixtures of Ni/tetraethyl silicate (TEOS) and conducting Ag powders were applied to fabricate the electrode by screen-printing processes. These processes are simple, low cost and easy to scale up for large sized panels. The field emission properties performed uniform emission image and high brightness (no less than 500 nits). The turn-on electric field was about 3.85 V/mu m with an emission current destiny of 10 mu A/cm(2), and the achieved current density was 1 mA/cm(2) driven by 5 V/mu m. (c) 2006 Elsevier B.V. All rights reserved.
  • Thumbnail Image
    Item type:Item,
    Multilayer MoS2 prepared by one-time and repeated chemical vapor depositions: anomalous Raman shifts and transistors with high ON/OFF ratio
    (2015-11-04)
    Wu, Chong-Rong
    ;
    Chang, Xiang-Rui
    ;
    Chang, Shu-Wei
    ;
    Chang, Chung-En
    ;
    Wu, Chao-Hsin
    We show that multilayer molybdenum disulfide (MoS2) grown with the chemical vapor deposition (CVD) may exhibit quite distinct behaviors of Raman shifts from those of exfoliated ones. The anomalous Raman shifts depend on CVD growth modes and are attributed to the modified dielectric screening and interlayer coupling of MoS2 in various growth conditions. With repeated CVD growths, we demonstrated the precise control over the layer number of MoS2. A decently large drain current, high ON/OFF ratio of 10(5), and enhanced field-effect mobility can be achieved in transistors fabricated on the six-layer MoS2.
  • Thumbnail Image
    Item type:Item,
    化學氣相沈積氮化鈦和鋁在極大型積體電路金屬連線之先導性研究
    (1995)
    蘇翔
    ;
    國立交通大學電子工程研究所
    本計畫以用化學氣相沈積方式作氮化鈦和 鋁的金屬化為研究主旨,氮化鈦在極大型積體 電路製程中用來防止鋁的擴散,作淺接面的接 觸.傳統方式鍍氮化鈦是用活性濺鍍(Reactivesputtering),也即用Ar離子來撞擊鈦,在反應腔內通 以氮氣,所以在沈積過程中就形成了氮化鈦,這 種方式在接觸洞(Contacthole)大於0.35微米時,尚 可應付所需,但小於0.35微米時,金屬與矽接觸的 可靠性就不敷所求,而化學氣相沈積最大的特 色就是Comformality,其Step coverage的能力不是用濺 鍍可相比的.所以本計畫研究的第一個目標是 用低壓化學氣相沈積設備來形成氮化鈦,所用 的原料有兩種,均為液態,用Carrier gas帶入反應腔以作沈積,原料為TDEAT和TDMAT,其沈積物理與電 性,將在本計畫作詳細分析,選用此種原料主要 原因是在沈積溫度450.degree.C以下仍有合理的沈 積率以便這種技術可適用於多層金屬連線的VIA ,基於同樣理由,用濺鍍方式無法達成鋁在接觸 洞的Step coverage需求,尤其是接觸洞的尺寸小於 0.25微米 而Aspect ratio又大於1.6時,化學氣相沈積 幾乎勢在必行,所以在化學氣相沈積氮化鈦之 後,再用化學氣相沈積鋁是一很自然的趨勢.本 計畫第二目標即為研究鋁化學氣相沈積之特性 .所用的原料也為液體,計畫選兩種原料作實驗, 利用蒸氣壓夠高,才能產生合理的沈積率,原料 為TIBAL和DMA1H,研究重點為物性、電性和元件製 程之相容性.其中以DMA1H最具潛力,因為它具有 選擇性沈積於金屬或矽的能力.在本計畫將對 鋁的選擇性沈積作一探討,本計畫以先期性研 究下一代極大型積體電路金屬連線和接觸技術 ,期望不僅在學術上對金屬化學沈積有所了解, 而且寄望在此領域對我國積體電路工業有所貢 獻.
  • Thumbnail Image
    Item type:Item,
    使用UHV/CVD低溫成長複晶矽於次微米元件之應 用
    (1995)
    雷添福
    ;
    LEI TAN-FU
    ;
    國立交通大學電子工程研究所
    本計畫將研究以"超高真空化學氣相沈積系 統"沈積複晶矽、複晶矽鍺和複晶矽硼之薄膜 成長.並研究這些複晶薄膜之材料物性及應用 於次微米元件之可行性.本計畫之研究可分為 五大主要部分進行,如下所述:(1)利用超高真空 化學氣相沈積系統成長複晶矽、複晶矽鍺,並 利用X-ray繞射、TEM、SEM、SIMS...等分析儀器研究 其材料特性及建立其成長機制;(2)我們將進一 步研究以超高真空化學氣相沈積系統成長複晶矽、複晶矽鍺應用於MOS元件及低溫製程元件之 可行性.並且探討藉由鍺在複晶矽鍺中不同的 含量來調制MOS元件之臨界電壓之特性;(3)我們 將提出一種新的製程技術來研製堆疊複晶矽接 觸淺接面二極體,利用超高真空化學氣相沈積 系統低溫沈積矽硼層於複晶矽上作為硼原子之 擴散源,來形成複晶矽接觸淺接面二極體.我們 將和傳統BF/sub 2//sup +/離子佈植方法形成之複 晶矽接觸二極體做分析與比較其電性特性及硼原子擴散分布之差異.再者,我們亦將利用此種 技術研製淺接面深度小於0.05.mu.m之複晶矽接觸 超淺接面二極體;(4)我們將提出一種新的製程 技術來研製正型(P-type)複晶矽閘極,即利用超高 真空化學氣相沈積系統沈積矽硼層於複晶矽上 作為硼原子擴散源來製作正型複晶矽閘極.我 們將和傳統以B/sup+/、BF/sub 2//sup +/離子佈植方 法做分析與比較硼原子穿透薄氧化層效應及正 型複晶矽閘極之電性特性;(5)研究以超高真空 化學氣相沈積系統沈積之矽硼層之氧化特性, 我們將建立矽硼層在乾氧、溼氧中氧化成長速 率氧化特性及氧化成長機制,我們亦將利用TEM 、SEM、FTIR分析其氧化層特性.此研究計畫完成 後,必然會進一步提升超大型積體電路製程技 術及改善次微米元件之特性.
  • Thumbnail Image
    Item type:Item,
  • Thumbnail Image
    Item type:Item,
    單晶之CVD薄膜和熔化成長法製程中的不穩定熱流與使其穩定之研究---總計畫(I)
    (1996)
    林清發
    ;
    LIN TSING-FA
    ;
    國立交通大學機械工程學系
  • Thumbnail Image
    Item type:Item,
  • Thumbnail Image
    Item type:Item,
  • Thumbnail Image
    Item type:Item,
    實用銅膜之化學氣相沈積技術研究
    (2001)
    陳茂傑
    ;
    交通大學電子工程系