學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Search Results

Now showing 1 - 10 of 25

The Impact of Layout Dependent Intrinsic Parasitic RLC on High Frequency Performance in 3T and 4T Multi-finger nMOSFETs
(2019-01-01)
Guo, Jyh-Chyurn
;
Ou, Jyun-Rong
;
Lin, Jinq-Min
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new observation of significant differences in the high frequency device parameters and performance like f(T) and f(MAX) is identified from the comparison of 3-terminal (3T) and 4-terminal (4T) multi-finger (MF) nMOSFETs. Through an extensive characterization on the intrinsic Z- and Y-parameters, it is found that the major impact comes from the particular increase of intrinsic parasitic resistances and inductances at the source terminal, namely R-s,R-int and L-s,L-int in the 4T MF MOSFETs. The proposed analytical models as a function of key device parameters incorporating the influence of the intrinsic parasitic RLC through high frequencies can accurately predict f(T) and f(MAX) degradation in 4T MF nMOSFETs as well as the complicated layout dependent effects. The experimental results and analytical models can be useful to facilitate MF devices layout optimization for high frequency design and performance improvement.
Very low noise in 90nm node RF MOSFETs using a new layout
(2007-01-01)
Kao, H. L.
;
Chin, Albert
;
Liao, C. C.
;
McAlister, S. P.
;
電子工程學系及電子研究所
We have directly measured a record low minimum noise figure (NFmin) of 0.46 dB at 10 GM, along with a high 16.6 dB Associated Gain, in an 8-finger 90 nm node MOSFET (L-G = 65nm) without de-embedding. At 18 GHz, NFmin was 0.83 dB with 13.5 dB gain. This was achieved using a microstrip line layout to screen the RF noise generated by the lossy substrate.
Impact of Highly Compressive Interlayer-Dielectric-SiNx Stressing Layer on 1/f Noise and Reliability of SiGe-Channel pMOSFETs
(2010-12-01)
Chen, Yu-Ting
;
Chen, Kun-Ming
;
Liao, Wen-Shiang
;
Huang, Guo-Wei
;
Huang, Fon-Shan
The 1/f noise and reliability of SiGe-channel pMOSFETs with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx stressing layer have been studied in this letter. The SiGe-channel devices with a highly compressive CESL layer have higher drain current and lower 1/f noise than the conventional SiGe-channel and bulk-Si devices. However, the device reliability is degraded while integrating with the highly compressive CESL layer. By examining the effective oxide-trap densities under hot-carrier instability stress, we find that the incorporated hydrogen in gate oxide during CESL layer deposition may play an important role on the 1/f noise and device reliability.
High-Performance GaN MOSFET With High-k LaAlO3/SiO2 Gate Dielectric
(2012-01-01)
Tsai, C. Y.
;
Wu, T. L.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Using a high-k LaAlO3/SiO2 gate dielectric, the recessed-gate GaN MOSFET has a low threshold voltage (V-t) of 0.1 V, low on-resistance (R-on) of 13.5 Omega . mm, high breakdown voltage of 385 V, high transconductance (g(m)) of 136 mS/mm, and record-best normalized drive current (mu C-ox) of 172 mu A/V-2. Such excellent device integrity is due to the small capacitance equivalent thickness of 3.0 nm, using a high-k gate dielectric and recessed-gate etching.
PBTI Investigation of MoS2 n-MOSFET With Al2O3 Gate Dielectric
(2017-05-01)
Yuan, Hui-Wen
;
Shen, Hui
;
Li, Jun-Jie
;
Shao, Jinhai
;
Huang, Daming
For the first time, we report the positive bias temperature instability of the back gated multilayer MoS2 n-MOSFETs with Al2O3 gate dielectric. In the stress phase, the Id-Vg curve shifts to the positive gate bias. In the recovery phase, it shifts back to the negative gate bias. After 5000 s recovery, it completely recovers to that of the fresh device. The results indicate that the voltage shift is solely due to trapping and detrapping of the pre-existing border traps in the Al2O3 dielectric. The traps consist of fast and slow components with the capture time constants of 7 and 1.8 x 10(2) s and the emission time constants of 15 and 1.0 x 10(3) s, respectively. The results from first-order trapping and detrapping calculations are in overall agreements with 12 measured Delta Vg curves including six under stress voltages and six in the recovery phases. The energy densities for the fast and slow traps are derived to be in the order of 10(13) cm(- 2) eV(-1) above the bottom of the MoS2 conduction band.
Analysis of abnormal transconductance in body-tied partially-depleted silicon-on-insulator n-MOSFETs
(2017-12-31)
Lin, Chien-Yu
;
Chang, Ting-Chang
;
Liu, Kuan-Ju
;
Chen, Li-Hui
;
Chen, Ching-En
This research investigates the mechanism of abnormal transconductance (Gm) and abnormal charge pumping current (I-CP) in body-tied partially-depleted silicon-on-insulator n-channel metal-oxide-semiconductor field effect transistors. The I-CP second hump region increases with channel length, yet is not affected by channel width. The cross-sectional view of the L-gate structure along the width direction demonstrates that a part of the poly gate area near the body contact is covered by a P+ implant, inducing a parasitic channel under the P+ poly gate. This parasitic channel leads to the abnormal Gm and I-CP hump, and such mechanism is further verified by body floating devices.
Investigation of Traps at MoS2/Al2O3 Interface in nMOSFETs by Low-Frequency Noise
(2016-04)
Yuan, Hui-Wen
;
Shen, Hui
;
Li, Jun-Jie
;
Shao, Jinhai
;
Huang, Daming
A new method is proposed to distinguish the contributions of the low-frequency noise (LFN) from the channel and the source/drain Schottky contacts in MOS devices. The method is applied to back-gated nMOSFETs with MoS2 channel and Al2O3 gate dielectric. To avoid a possible noise signal contamination from the top MoS2 surface by oxygen or water molecules absorption, the nMOSFETs with multilayer MoS2 are fabricated, and the measurements are carried out in the vacuum. The trap density Not at the MoS2/Al2O3 interface is derived for the first time using the proposed method. It is found that the Not responsible to LFN depends strongly on the surface potential, ranging from 4 x 10(10) cm(-2) in the weak over-drive region to 5 x 10(11) cm(-2) in the strong over-drive region.
Effects of In-Situ Plasma-Enhanced Atomic Layer Deposition Treatment on the Performance of HfO2/In0.53Ga0.47As Metal-Oxide-Semiconductor Field-Effect Transistors
(2016-08)
Quang Ho Luc
;
Cheng, Shou Po
;
Chang, Po Chun
;
Huy Binh Do
;
Chen, Jin Han
In-situ plasma-enhanced atomic layer deposition (PEALD) technique was employed for device passivation to realize a high-performance inversion-mode HfO2/In0.53Ga0.47As metal-oxide-semiconductor field-effect transistor (MOSFET). Excellent quality of gate dielectric is enabled by utilizing the PEALD-aluminum nitride as a pre-gate interfacial layer, followed by a post-gate remote-plasma gas treatment. In-situ PEALD treatment led to enhanced dc characteristics, such as drain current, peak transconductance, subthreshold swing, OFF leakage current, and effective electron mobility. X-ray photoelectron spectroscopy analysis indicates a reduction of In-and Ga-related signals. Furthermore, small drain current hysteresis and low-interface state density (D-it) value confirm a high interfacial quality for the high-k/III-V structure. Overall, the PEALD passivation for HfO2/In0.53Ga0.47As interface shows a remarkable improvement on the MOSFET performance.
Impact of Inner Pickup on ESD Robustness of Multifinger MOSFET in 28-nm High-k/Metal Gate CMOS Process
(2015-12-01)
Lin, Chun-Yu
;
Chang, Pin-Hsin
;
Chang, Rong-Kun
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The impact of pickup structure on electrostatic discharge (ESD) robustness of multifinger MOSFET in 28-nm high-k/metal gate CMOS process was investigated in this paper. Verified in silicon, the multifinger MOSFET without the pickup structure inserted into its source region can sustain the higher ESD level and more compact layout area.
金屬閘極/高介電係數材料互補式金氧半場效電晶體在45到22奈米世代之應用(I)
(2008)
荊鳳德
;
CHIN ALBERT
;
國立交通大學電子工程學系及電子研究所
發展金屬閘極/高介電質技術對45nm節點的CMOSFET而言是必須的，因為此技術可用來減少閘極漏電流，以減少直流功率消耗。Intel的共同創辦人，摩爾定律的發明者Golden Moore認為，金屬閘極/高介電質技術是過去四十年來電晶體最重要的發明，這項重要的發明相當可能得到諾貝爾獎。我們是高閘極介電質領域的先驅者之一，早在1998年就開始此領域上的研究，我們研究過的介電質如Al2O3、La(Al)O3、HfLaO(N)已被世界各地的研究者所引用，包括IBM及H. Iwai教授(IEEE Electron Devices前主席，Eber＇s獎的所有人)等。目前HfO-based的高介電質已被Intel用來作45nm節點電晶體的閘極介電質，其等效氧化層厚度(equivalent-oxide-thickness；EOT)只有1~1.2nm，若要進一步的將技術推進至32nm或22nm節點，需要將高介電質的EOT進一步的降至1nm以下。不幸的是，HfO2的導帶差(EC)較小，造成較高的漏電流，為了因應此問題，需使用鑭系的閘極介電質或HfLaON，因為HfLaON之EC(2.3eV)較HfO2(1.5eV)高，鑭系介電質的重要性可從SELETE和IMEC的研究以及他們在2007年12月於IEDM發表的論文中得到證實。金屬閘極/高介電質技術所遇到的挑戰還有高的臨限電壓(Vt)，這是因為介面反應和氧缺陷造成的Fermi level pinning，會使Vt升高。對PMOS而言要克服此一難關更為困難，因為只有Ir 和 Pt具備夠高的功函數(理想狀態要大於5.2eV)，然而，Pt很難用RIE蝕刻，而Ir在高介電質HfSiON上則很不穩定，我們之前曾發展出熱穩定性高、和CMOS製成相容、富含Ir的金屬矽化物。因此本計劃第一年的目標是發展雙金屬閘極/高CMOSFET，其中我們用高熱穩定性、富含Ir的金屬矽化物當p – MOSFET的閘極，用HfSi當n – MOSFET的閘極。其EOT約為1.1~1.2nm，以使得功函數跟目標值(4.1和5.2eV)的差距在0.2 eV以內；n – MOSFET和p – MOSFET的遷移率分別應大於200和80 cm2/Vs；在85 oC下給予持續1小時、10MV/cm的偏壓，其偏壓溫度不穩定性(Bias-Temperature Instability；BTI)須小於50mV，以得到好的可靠度。第二年和第三年的目標則希望進一步把等效氧化層厚度下降到0.7~1.0nm，且功函數和目標值的差値仍要在0.2 eV以內。我們使用HfLaO和覆蓋鑭系元素的HfSiON來達到如此薄的EOT，而且僅伴隨著少許Fermi-level pinning。這是目前所知唯一能達到目標的方法，目前有SELETE-Japan，IMEC，SNDL 以及我們曾使用過。這麼薄的EOT下，薄的base oxide和remote scaling會把遷移率降到100~150 cm2/Vs，然而即使在此情形下，將電路操作在85 oC，給予持續1小時10MV/cm的偏壓，仍能得到小於50mV的BTI。要達到上述的規格，必須作詳細的介面和氧空穴(vacancy)的分析，我們團隊中材料科學和介面特性的專家將負責此部份。此外，耶魯大學的T. P. Ma教授也會與我們合作並給我們建議以達成此目標。

學術出版;;Publications

Browse

Filters

Settings

Sort By

Results per page

🏛️國立陽明交通大學機構典藏

Search Results