學術出版;;Publications

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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Now showing 1 - 10 of 35

Planar constrained terminals over-the-cell router
(1997-03-01)
Shew, PW
;
Hsiao, PY
;
資訊工程學系
;
Department of Computer Science
The authors present a new routing model for over-the-cell channel routing. A graph theoretical algorithm is then proposed to solve the new problem, The algorithm has a complexity of O(nk(2)), where n is the number of nets and k is the number of columns in the channel. It achieved a routing area reduction of 71.5% for the PRIMARY 1 benchmark example from MCNC, using three-layer over-the-cell routing. To resolve a sub-problem, the authors also present an O(m nu) algorithm to find the maximum weight independent chord set in a circle graph with m chords incident to nu vertices, where two chords may share a common vertex.
AN OPTIMAL PARALLEL ALGORITHM FOR GENERATING PERMUTATIONS IN MINIMAL CHANGE ORDER
(1994-03-01)
TSAY, JC
;
LEE, WP
;
資訊工程學系
;
Department of Computer Science
Permutation generation is an important problem in combinatorial computing. In this paper we present an optimal parallel algorithm to generate all N! permutations of N objects. The algorithm is designed to be executed on a very simple computation model that is a linear array with N identical processors. Because of the simplicity and regularity of the processors, the model is very suitable for VLSI implementation. Another advantageous characteristic of this design is that it can generate all the permutations in minimal change order.
Accurate performance evaluation of VLSI designs with selected CMOS process parameters
(2018-01-01)
Chang, Chia-Ling (Lynn)
;
Wen, Charles H. -P.
;
電機工程學系
;
Department of Electrical and Computer Engineering
As process monitors have become vital components in modern very-large-scale integration (VSLI) designs, performance targets often determine the physical implementation of such monitors. However, as various process and environmental parameters collectively affect circuit behaviour, the design of process monitors can be difficult. In addition, process parameters from device-level models may not provide sufficient resolution in circuit-level performance. Therefore, the authors propose an intelligent novel flow for selecting dominant process parameters for evaluating performance targets such as timing and leakage. The proposed flow is applied to ISCAS'85, ISCAS'89, and IWLS'05 benchmark circuits and selects the dominant parameters in 32 and 45nm complementary metal-oxide-semiconductor (CMOS) technologies. Through this flow, the authors identify the supply voltage, temperature, gate-oxide thickness, and effective gate length as the four dominant factors for timing and leakage. Experimental results show that the suggested process parameters achieve high evaluation accuracy (<3% errors in timing and <1% errors in leakage on average) in the benchmark circuits. Therefore, the proposed flow can select dominant parameters for performance targets, and the four determined factors can be used to accurately evaluate timing and leakage in 32 and 45nm CMOS technologies.
New Recoding Methods for Fully Pipelined Parallel CORDIC Rotations
(2015)
Juang, Tso-Bing
;
Chiu, Chin-Chieh
;
資訊工程學系
;
Department of Computer Science
In this paper, new recoding methods for fully pipelined parallel CORDIC (COordinate Rotation DIgital Computer) are proposed. By employing new proposed MAR (Micro-rotation to Angle Recoding), fully pipelined parallel CORDIC rotation schemes can be obtained so that they can reduce the bottleneck of conventional parallel CORDIC rotators which have two separate micro-rotation stages. Although our proposed methods would produce more micro-ration stages compared with previous methods, these stages can be further merged to save area costs and to enhance the overall performance of CORDIC rotations. Our proposed methods can be applied to sine/ cosine generators, DDFS (Direct Digital Frequency Synthesizer) and other related applications for fast computations.
A Multi-Bin Constant Throughput CABAC Decoder for HEVC
(2015)
Chen, Hsuan-Ku
;
Fang, Chih-Chung
;
Chang, Tian Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a CABAC decoder for HEVC that achieves constant high throughput multi-bin decoding with the parallel syntax element parser to solve the dependency problem in the traditional prediction based multi-bin architecture. The hardware implementation with TSMC 90nm CMOS technology can process 1 bins per cycles with 48,430 gate count (270Mbins/sec,) or 3 bins per cycle with 209,422 gate count (810Mbins/sec) when operating at 270MHz.
超大型積體電路設計與計算機自動輔助設計---總計畫
(1993)
李崇仁
;
任建葳
;
交通大學電子研究所
利用「共用乘法器」演算法的八乘八離散餘弦轉換的超大型積體電路製作
(1993)
沈文仁
;
交通大學電子研究所
與傳統電視系統相較,高畫質電視(HDTV)是一種具有高品質畫面及嚴響的電視系統.在傳輸這些 HDTV信號之前,我們需利用數據壓縮(Data Compression) 的技術將信號壓縮以減少所需的傳輸頻寬.離散餘弦轉換(Discrete Consine Transform, DCT)即是HDTV系統所用的壓縮技術.本計畫中,我們根據「共用乘法器」的演算法,完成超大型積體電路的製作.以前所設計成功之DCT電路,轉換速度太慢,無法滿足HDTV系統的要求(70MHZ以上).本計畫即是根據我們所提出的新的演算法,完成實際的電路設計,其資料處理速度在70MHZ以上,電路的面積要小於1平方公分.
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture
(2015-10-01)
Lin, Chia-Lung
;
Chen, Chih-Lung
;
Chang, Hsie-Chia
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
In this paper, a design approach for architecture-aware nonbinary low-density parity-check convolutional codes (NB-LDPC-CCs) is presented to jointly optimizes the code performance and decoder complexity for achieving high energy-efficiency decoder. The proposed NB-LDPC-CCs not only feature simple structure and low degree, but also compete with other published NB-LDPC-CCs on error-correction capability. With these codes, we present a memory-based layered decoder architecture, where the computation units and the scheduling of the computations are optimized to increase energy efficiency. To demonstrate the feasibility of proposed techniques, a time-varying (50,2,4) NB-LDPC-CC over GF(256) is constructed, and associated decoder is implemented in 90 nm CMOS. The code can reach BER = 10(-5) at SNR = 0.9 dB, and support multi code rates with puncturing. Comparing with the state-of-the-art designs, the proposed decoder can save 74% power under the same number of iterations, making it suitable for emerging Internet of Things (IoT) applications.
高密度電漿源設計製作及其應用在半導體製程發展(III)
(2000)
蔡春鴻
;
C.H.Tsai
;
交通大學電信工程系
即時數位視訊傳輸系統之設計
(1994)
溫?岸
;
國立交通大學電子工程研究所
視訊傳輸的應用至廣,毋庸列舉,隨著數位通訊系統的日漸廣泛,數位化視訊系統近年來亦在HDTV研發計畫之下倍受資訊及通訊業界重視. 依據以往從事視訊壓縮技術的研發及電路設計 ,我們曾經嘗試以多種方式,如3D-DCT, 3D-subband hybridVQ...等,於影像序列作編解碼,再將完成解碼之序列播放,其結果顯示,以各種技術相互搭配有助於品質的提昇,再者,對於序列影像的品質評估,因為人類視覺、心理多種主觀因素影響,其比較判別無法以一般量化數值如SNR等為斷,勢必要眼見為評.因此,為求具體實用的數位化視訊傳輸系統設計,我們擬結合高階技術模擬系統以至於EDA電路設計自動化工作站建立一整合設計環境,經由模擬系統作技術研擬,效能觀測及系統規格之制定,再藉由運算流程的分析,即時傳輸的配合考量,提供電路設計的規格. 在一年期的計畫中,模擬系統將採用Sparc工作站及DSP/PC工作站兩種目前最普遍的運算工作站, 傳輸技術則將採用:(1)混合型向量量化(Hybrid VQ) ;(2)3D-分頻瀘波(3-Subband);(3)3D-DCT;(4)DPCM等技術, 以上視訊壓縮技術經由研究測試,對於視訊處理的效能良好,結構性亦佳.電路系統設計則將以電腦網路及電話線路為目標,完成之電路設計可藉由實際通訊通道獲致驗證評估,亦可提供具體實用之即時數位視訊傳輸系統.

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