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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Access type: Open accessAuthor: search.filters.author.CHEN, LJ

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Now showing 1 - 4 of 4
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    ENHANCEMENT OF OXIDE BREAK-UP BY IMPLANTATION OF FLUORINE IN POLY-SI EMITTER CONTACTED P-+-N SHALLOW JUNCTION FORMATION
    (1994-04-01)
    WU, SL
    ;
    LEE, CL
    ;
    LEI, TF
    ;
    CHEN, CF
    ;
    CHEN, LJ
    In this study, it is demonstrated that the incorporation of fluorine can enhance poly-Si/Si interfacial oxide break-up in the poly-Si emitter contacted p+-n shallow junction formation. The annealing temperature for breaking up the poly-Si/Si interfacial oxide has been found to be as low as 900-degrees-C. As a result, the junction depth of the BF2-implanted device is much larger than that of the boron-implanted device.
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    SUPPRESSION OF THE BORON PENETRATION INDUCED SI/SIO2 INTERFACE DEGRADATION BY USING A STACKED-AMORPHOUS-SILICON FILM AS THE GATE STRUCTURE FOR PMOSFET
    (1994-05-01)
    WU, SL
    ;
    LEE, CL
    ;
    LEI, TF
    ;
    CHEN, JF
    ;
    CHEN, LJ
    This letter reports that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO2 interface. An atomically flat Si/SiO2 interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p+ poly-Si gate MOS devices even the annealing temperature is as high as 1000-degrees-C.
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    INVESTIGATION ON THE DISTRIBUTION OF FLUORINE AND BORON IN POLYCRYSTALLINE SILICON SILICON SYSTEMS
    (1995-06-01)
    CHEN, TP
    ;
    LEI, TF
    ;
    CHANG, CY
    ;
    HSIEH, WY
    ;
    CHEN, LJ
    The behaviors of fluorine in BF2+ implanted polycrystalline silicon (poly-Si) on silicon have been investigated in the annealing temperature range of 850 to 1100 degrees C. The distribution of fluorine atoms as functions of temperature and time have been monitored by the secondary ion mass spectroscopy (SIMS) and cross-sectional transmission electron microscopy (XTEM). The XTEM micrographs revealed that fluorine bubbles are distributed in the poly-Si and at the original poly-Si/Si interface after annealing. The locations of bubbles were found to correspond to the fluorine peaks in the SIMS depth-concentration profiles. The presence of the boron peak at the original poly-Si/Si interface is attributed to the gettering of boron atoms by the fluorine bubbles. Moreover, the boron profiles in the silicon substrates are sensitive to thermal budget due to the pileup of fluorine atoms at the poly-Si/Si interface. The pileup of fluorine at the poly-Si/Si interface leads to an enhancement of epitaxial regrowth of poly-Si films and. the formation of fluorine bubbles. Consequently higher surface dopant concentration and deeper junction depth were obtained.
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    A COMPREHENSIVE STUDY OF SUPPRESSION OF BORON PENETRATION BY AMORPHOUS-SI GATE IN P+-GATE PMOS DEVICES
    (1995-12-01)
    LIN, CY
    ;
    JUAN, KC
    ;
    CHANG, CY
    ;
    PAN, FM
    ;
    CHOU, PF
    This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p(+)-gate devices, The characteristics and reliability for different gate structures (poly-Si, alpha-Si, poly-Si/poly-Si, poly-Si/alpha-Si, alpha-Si/poly-Si, and alpha-Si/alpha-Si) in p(+) polygate PMOS devices are investigated in detail, The suppression of boron penetration by the nitrided gate oxide is also discussed, The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p(+) polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate, Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance, The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p(+)-gate PMOS device for future dual-gate CMOS process, In addition, by employing a long time annealing at 600 degrees C prior to p(+)-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate, Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect.