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Direct oxidation of Si1-xGex layers using Vacuum-Ultra-Violet light radiation in oxygen
(1998-02-01)
Chen, LP
;
Chan, YC
;
Chang, SJ
;
Huang, GW
;
Chang, CY
Oxidation of Si1-xGex films has been carried out by direct photo chemical Vapor deposition (direct photo-CVD) directly with activated O-2 induced by Vacuum-Ultra-Violet (VUV) light radiation, The Auger electron spectroscopy profiles show that no Ge-pileup layer at the oxide/Si1-xGex interface is observed after VUV-induced Si1-xGex oxidation process. The X-ray photoelectron spectroscopy analysis of the samples reveals that Si and Ge are oxidized simultaneously in oxidation process and a mixed oxide layer consisting both SiO2 and GeO2 is formed, This might be the reason that Cc pileup effect is eliminated in this study.
Deposition of polycrystalline Si and SiGe by ultra-high vacuum chemical molecular epitaxy
(2000-07-01)
Chen, KM
;
Huang, HJ
;
Chang, CY
;
Chen, LP
;
Huang, GW
The polycrystalline Si1-xGex (poly-Si1-xGex) films have better properties than poly-Si for device fabrications, such as lower proceeding temperature and process thermal budget. For these reasons, the poly-Si1-xGex films have been utilized for low-temperature thin film transistor fabrications and gate electrodes of metal-oxide-semiconductor transistors. In this work, disilane and germane were used to grow poly-Si1-xGex films at low temperature (<600 degrees C) by the cold-wall type ultrahigh vacuum chemical molecular epitaxy system. The poly-Si1-xGex films were deposited on oxide and nitride surfaces. The Ge fraction x was evaluated from x-ray diffraction and Auger electron spectroscopy. It is observed that the Ge fraction increases with the increase of the GeH4 flow rate. The result is only slightly related to the substrate type. The growth rate increases with the Ge fraction at lower values and then decreases with the Ge fraction in the higher composition range. This implies that the growth mechanism of poly-Si1-xGex films is different from that of epitaxial Si1-xGex on Si. The uniformity of poly-Si1-xGex films depends on the Ge fraction, and it is improved-by the addition of germanium. The result can be explained by the lower activation energy (<0.25 eV) of poly-Si(1-x)G(x), deposition as compared to that of poly-Si (similar to 2.1 eV). From the x-ray diffraction and atomic force microscopy analyses, the crystallinity and surface roughness of films are suitable for device fabrications. (C) 2000 American Vacuum Society. [S0734-2101(00)07704-6].
Study of boron effects on the reaction of Co and Si1-xGex at various temperatures
(2000-07-01)
Huang, HJ
;
Chen, KM
;
Chang, CY
;
Huang, TY
;
Chang, TC
The effects of boron on Co and Si1-xGex interfacial reaction were studied. Undoped and ill situ boron-doped strained Si0.91Ge0.09 and Si0.86Ge0.14 layers prepared at 550 degrees C by an ultrahigh vacuum chemical vapor deposition system were subjected to Co silicidation at various rapid thermal annealing (RTA) temperatures ranging from 500 to 1000 degrees C. The resulting films were characterized by a sheet resistance measurement, Auger electron spectroscopy, x-ray diffractometry (XRD), high resolution x-ray diffractometry, secondary ion mass spectroscopy, scanning electron microscopy, and transmission electron microscopy. Seen from XRD spectroscopy, a Co(Si1-yGey) cubic structure was formed with RTAs ranging from 500 to 700 degrees C. For boron-doped samples, the CoGe fraction in Co(Si1-yGey) was less than that in undoped samples, indicating that baron atoms retarded the incorporation of Ge into the Co(Si1-yGey) ternary phase. It also led to a large Ge pileup at the interface between the Co-rich and silicidation regions. On the other hand, from the high resolution x-ray spectra, the presence of boron led to less relaxation of the strained Si1-xGex lattice. It is the first time that small boron atoms inhibiting the relaxation of the Si1-xGex layer during silicidation was observed. Furthermore, from the sheet resistance measurement, the formation of CoSi2 was found to be slightly retarded in boron-doped samples, due probably to the decrease of Co or Si diffusivities as a result of boron accumulation at the Co/SiGe reaction interface. At temperatures above 800 degrees C, CoSi2 formed and Ge segregated to the silicide boundaries and the upper reaction region was discovered. These phenomena caused by B dopants are explained in detail. (C) 2000 American Vacuum Society. [S0734-2101(00)04604-2].
Effect of coplanar probe pad design on noise figures of 0.35 mu m MOSFETs
(2000-07-20)
Su, CY
;
Chen, LP
;
Chang, SJ
;
Huang, GW
;
Ho, YP
The effects of different coplanar ground-signal-ground (GSG) probe pads on the noise figure characteristics of submicron MOSFETs are presented. Devices with top-level metal as probe pads shielded by grounded bottom-level metal possess the most appropriate probe pad structure for characterising the noise performance of MOSFETs. Equivalent circuits of the probe pads are used to explain the different noise behaviours.
Study on Ge/Si ratio, silicidation, and strain relaxation of high temperature sputtered Co/Si1-xGex structures
(2000-08-15)
Huang, HJ
;
Chen, KM
;
Chang, CY
;
Huang, TY
;
Chen, LP
As the transistors continue to scale down, the characteristics of high-temperature-sputtered Co/Si1-xGex junction have received lots of attention because of its potential applications to heterojunction bipolar transistors. In this study, we have fabricated Co/Si1-xGex junction using room-temperature and high-temperature (i.e., at 450 degrees C) sputtered Co on top of strained Si0.86Ge0.14 and Si0.91Ge0.09 layers prepared by ultrahigh vacuum chemical molecular epitaxy. The relative composition of Ge in Ge-rich Si1-zGez precipitate and the solid solution of ternary phase silicide of Co-Si-Ge system were compared between room-temperature and high-temperature sputtered samples. We found that the high-temperature-sputtered samples are more effective in inhibiting lattice relaxation, which would be beneficial for manufacturing metal silicide/Si1-xGex structure devices. Mechanisms were proposed to explain the large difference between the room-temperature and high-temperature sputtered samples. It is believed that the mixed Co-Si-Ge solution on high-temperature-sputtered samples is responsible for the different silicidation behaviors. (C) 2000 American Institute of Physics. [S0021-8979(00)02616-5].
Reduction of source/drain series resistance and its impact on device performance for PMOS transistors with raised Si1-xGex source/drain
(2000-09-01)
Huang, HJ
;
Chen, KM
;
Chang, CY
;
Chen, LP
;
Huang, GW
P-channel MOS transistors with raised Si1-xGex and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impacts of Si1-xGex and Si epitaxial S/D layer on SID series resistance and drain current of p-channel transistors were studied. Our result show that the new device with Si1-xGex raised S/D layer depicts only half the value of the specific contact resistivity and S/D series resistance (R-SD), compared to the device with Si raised S/D layer. The improvement is even more dramatic, when comparing to the conventional device without any raised Sin layer i.e., R-SD of the new device with Si1-xGex raised S/D is only about one fourth the value of the conventional device. Moreover, the device with raised SiGe S/D structure produces a 29% improvement in transconductance (g(m)) at an effective channel length of 0.16 mu m, These performance improvements, together with several inherent advantages such as self-aligned selective epitaxial growth (SEG) nature and the resultant T-shaped gate structure, make the new device with raised Si1-xGex S/D structure very attractive for future sub-0.1 mu m p-channel MOS transistors.
The reaction of Co and Si1-xGex for MOSFET with poly-Si1-xGex gate
(2001-03-01)
Chen, KM
;
Huang, HJ
;
Chang, CY
;
Huang, TY
;
Huang, GW
The effects of Ge on the interfacial reaction between Co and poly-Si1-xGex materials were studied. Poly-Si1-xGex layers prepared at 580 degreesC by ultra-high vacuum chemical molecular epitaxy (UHVCME) system were subjected to Co silicidation at various rapid thermal annealing (RTA) temperatures ranging from 500 to 900 degreesC. From X-ray diffractometry (XRD), Co(Si1-xGex) cubic structure was formed with RTA temperature ranging from 500 to 800 degreesC for x = 0.09, while CoSi2 was formed at 900 degreesC. However, for x = 0.21, Co(Si1-yGey) persisted even after 900 degreesC RTA annealing, and CoSi2 was not found. These results indicate that Ge atoms retard the formation of CoSi2, As a result, the RTA temperature needed to obtain low sheet resistance has to be increased with increasing Ge content. Finally, p-channel metal-oxide-semiconductor (MOS) transistors with poly-Si1-xGex-gate have been successfully integrated with Co salicidation process. (C) 2001 Elsevier Science B.V. All rights reserved.
Improved low temperature characteristics of p-channel MOSFETs with Si1-xGex raised source and drain
(2001-08-01)
Huang, HJ
;
Chen, KM
;
Huang, TY
;
Chao, TS
;
Huang, GW
P-channel metal-oxide-semiconductor field-effect transistors with Si1-xGex raised source and drain (RSD) have been fabricated and further studied for low temperature applications. The Si1-xGex RSD layer was selectively grown by ANELVA. SRE-612 ultra-high vacuum chemical vapor deposition (UHVCVD) system, Compared to devices with conventional Si RSD, improved transconductance and specific contact resistance were obtained, and these improvements become even more dramatic with reducing channel length, Well-behaved short channel characteristics with reduced drain-induced barrier lowering (DIBL) and off-state leakage current are demonstrated on devices with 100 nm Si1-xGex RSD, due to the resultant shallow junction and less implantation damage. Moreover, temperature measurements reveal that Si1-xGex RSD devices show more dramatic improvement in device performance at low temperature (-50 degreesC) operation, which can be ascribed to the higher temperature sensitivity of the Si1-xGex sheet resistance.
A method to characterize the dielectric and interfacial properties of metal-insulator-semiconductor structures by microwave measurement
(2002-04-15)
Lue, HT
;
Tseng, TY
;
Huang, GW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have developed a method to investigate the dielectric and interfacial properties of gate dielectric thin films by microwave measurement. Ba0.5Sr0.5TiO3 (BST) thin films were deposited on 10 Omega cm (normal) and 10 k Omega cm [high-resistivity, (HR)] silicon substrates at the same time by rf magnetron sputtering. For the BST/HR-silicon, coplanar waveguides (CPW) were fabricated and measured at microwave frequencies with thru-reflect-line calibration while capacitance (C-V) measurements were carried out for BST/normal silicon. From the phase change of CPW transmission line and the maximum capacitance in C-V measurement, the dielectric constants of both the BST thin film and interface layer can be determined. Furthermore, the behaviors of insertion loss versus bias voltage were investigated. The results indicate that our method can provide useful information to study the dielectric and interfacial properties of metal-insulator-semiconductor structures. (C) 2002 American Institute of Physics.
A macro model of silicon spiral inductor
(2002-05-01)
Su, CY
;
Chen, LP
;
Chang, SJ
;
Tseng, BM
;
Lin, DC
A new automatic parameter extraction method for modeling Of silicon Spiral inductors is presented. The Concepts on self-resonance frequency (f(sr)) and quality factor of a spiral inductor are utilized to develop the concise extraction procedures. In the mean time, the presented extraction procedures are programmed as a macro to execute all the extractions automatically and shorten the extraction time effectively. Without any additional optimization or curve fitting, almost all the patterns of S-parameters between the measured and the simulation of extracted data implemented with the extraction macro are less than 5%. The programmed extraction macro makes it fast and accurate to extract and characterize the behaviours or silicon-based spiral inductors with different structures and substrate resistivities. It provides a concrete foundation commercial silicon radiofrequency (RF) Circuit design to realizing on-chip silicon RF integrated circuits. Furthermore, the directly extracted equivalent model parameters, without an optimization, also provide a rule to fairly, effectively and phsically judge the performance of a spiral inductor. (C) 2002 Elsevier Science Ltd. All rights reserved.

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