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Discrete-dopant-fluctuated threshold voltage roll-off in sub-16 nm bulk fin-type field effect transistors
(2008-04-01)
Li, Yiming
;
Hwang, Chih-Hong
;
電信工程研究所
;
Institute of Communications Engineering
The effect of the number and position of discrete dopants on device characteristics is crucial in determining the behavior of nanoscale semiconductor devices. We explore the fluctuations of threshold voltage (V(th)) roll-off in nanoscale bulk fin-type field effect transistors (FinFETs) by a three-dimensional (3D) statistically full-scale "atomistic" device simulation technique. The explored devices are of three different dimensions: 16, 22, and 30 nm(3). Discrete dopants are statistically positioned into the 3D channel region to explore associated carrier transport characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". For the device with a gate length of 16 nm, the V(th) fluctuation of FinFETs is only half that of planar metal-oxide-semiconductor (MOS) FET. Compared with planar MOSFETs, the bulk FinFETs can significantly suppress the fluctuation of V(th) roll-off. The standard deviation of V(th) is proportional to (WL)(-0.25), which is better than the (WL)(-0.5) of planar devices. The superior immunity against fluctuation and the stable fluctuation of V(th) roll-off indicate the bulk FinFET to be a promising device for the sub-16 nm technology era.
Large-scale "atomistic" approach to discrete-dopant-induced characteristic fluctuations in silicon nanowire transistors
(2008-06-01)
Li, Yiming
;
Hwang, Chih-Hong
;
Huang, Hsuan-Ming
;
電信工程研究所
;
Institute of Communications Engineering
Nanowire fin-typed field effect transistors (FinFETs) are ultimate structures and potential candidates for next generation nanoelectronic devices. Due to the limitation of manufacturability, nanowire transistors with a perfect gate structure (i.e., a surrounding gate with 100% gate-coverage ratio) theoretically are not always guaranteed. Impact of the discrete dopants on device performance is crucial in determining the behaviour of nanoscale semiconductor devices. The immunity of nanowire transistor against random discrete-dopant-induced fluctuation may suffer from the variation of gate-coverage-ratio. Therefore, in this paper, we for the fist time study the impact of non-ideal gate coverage on immunity against random-dopant-induced fluctuations for nanowire FinFETs. A 3D statistically sound "atomistic" approach for analyzing random-dopant effect in nanodevice is presented. Discrete dopants are statistically positioned into the channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Our results confirm that the influence of non-ideal gate coverage disturbs the,channel controllability of nanowire FinFETs and thus decreases the immunity against discrete-dopant-induced fluctuation. This study provides an insight into them problem of fluctuation in nanowire transistors and,shows the importance of gate-coverage ratio on device's immunity against discrete-dopant-induced fluctuation. (C) 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Discrete-Dopant-Fluctuated Transient Behavior and Variability Suppression in 16-nm-Gate Complementary Metal-Oxide-Semiconductor Field-Effect Transistors
(2009-04-01)
Li, Yiming
;
Hwang, Chih-Hong
;
Cheng, Hui-Wen
;
電信工程研究所
;
Institute of Communications Engineering
Variability in the characteristics of nanoscale complementary metal-oxide-semiconductor (CMOS) field-effect transistors is a major challenge to scaling and integration. However, little attention has been focused on the existence of transient behavior fluctuations of devices owing to random dopant placement. In this study, we explore the discrete-dopant-induced transient behavior fluctuations of 16-nm-gate CMOS circuits through a three-dimensional large-scale statistically sound "atomistic" device-circuit-coupled simulation approach, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". For a 16-nm-gate CMOS inverter, a 3.5% variation of the rise time, a 2.4% variation of the fall time, an 18.3% variation of the high-to-low delay time, and a 13.2% variation of the low-to-high delay time are estimated and discussed. Fluctuation suppression techniques proposed from the device and the circuit viewpoints are implemented to examine the associated intrinsic fluctuations. (C) 2009 The Japan Society of Applied Physics
Temperature dependence on the contact size of GeSbTe films for phase change memories
(2008-09-01)
Li, Yiming
;
Yu, Shao-Ming
;
Hwang, Chih-Hong
;
Kuo, Yi-Ting
;
資訊工程學系
In this study, a three-dimensional electro-thermal time-domain simulation is developed for dynamic thermal analysis of Phase change memories (PCMs). The geometry effects of the GeSbTe (GST) materials and the TiN heater are explored through a series of numerical examinations. It is found that the contact size of the GST significantly alters the maximum temperature of the PCMs, compared with the height of the GST films. The heater's aspect ratio also dominates the maximum temperature of the GST material, and the effect of the heater's thickness on the temperature is more evident than its height. One conformal bi-layer GST structure with different electric and thermal conductivities on the GST layers is examined for different applied currents to extract the curve of resistances versus applied currents.
Process-Variation- and Random-Dopant-Induced Static Noise Margin Fluctuation in Nanoscale CMOS and FinFET SRAM Cells
(2009)
Li, Tien-Yeh
;
Hwang, Chih-Hong
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this study, a three-dimensional "atomistic" coupled device-circuit simulation approach is advanced to investigate the process-variation-effect (PVE) and random dopant fluctuation (RDF) induced characteristic fluctuations in planar metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) from 65-nm to 16-nm gate length. Our preliminary results show that the RDF dominates the fluctuation of static noise margin (SNM). As the gate length of the planar MOSFETs scales from 65 nm to 16 nm, the normalized RDF-induced SNM fluctuation increases from 4% to 80%. To reduce the device variability induced fluctuation in circuit, a device with vertical-doping-profile and raised V(th) is employed. The SNM is 3 times larger than the original 16-nm-gate SRAM. Moreover, the normalized RDF-induced SNM fluctuation is reduced by a factor of 2.67. Additionally, a 16-nm-gate silicon-on-insulator fin-type field-effect-transistor is used to further improve the SNM of SRAM. Due to the superior electrostatic integrity and larger effective device width than planar MOSFETs, the SNM of 16-nm-gate FinFET SRAM is six times larger than the original 16 nm SRAM with five times smaller SNM fluctuation. The study investigates the roll-off characteristics of SNM and provides an insight into design of fluctuation resistant nanoscale SRAM.
Large-Scale Atomistic Circuit-Device Coupled Simulation of Discrete-Dopant-Induced Characteristic Fluctuation in Nano-CMOS Digital Circuits
(2010)
Li, Yiming
;
Hwang, Chih-Hong
;
電信工程研究所
;
Institute of Communications Engineering
The increasing characteristics variability in nano-CMOS devices becomes a major challenge to scaling and integration. In this work, a large-scale statistically sound "atomistic" circuit-device coupled simulation methodology is presented to explore the discrete-dopant-induced characteristic fluctuations in nano-CMOS digital circuits. According to the simulation scenario, the discrete-dopant-induced characteristic fluctuations are examined for a 16-nm-gate MOSFET and inverter circuit. The fluctuations of the intrinsic current-voltage and capacitance-voltage characteristics, and timing behaviors for the explored device and circuit are estimated. The timing fluctuation may result in a significant signal delay in the digital circuit. Consequently, links should be established between circuit design and fundamental device technology to allow circuits and systems to accommodate the individual behavior of every transistor on a silicon chip. The proposed simulation approach could be extended to outlook the fluctuations in various digital and analog circuits.
Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale planar MOSFET and bulk FinFET devices
(2009-03-01)
Li, Yiming
;
Hwang, Chih-Hong
;
Cheng, Hui-Wen
;
電信工程研究所
;
Institute of Communications Engineering
Impact of the intrinsic fluctuations on device characteristics, such as the threshold voltage (V(th)) fluctuation is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the dependency of process-variation and random-dopant-induced V(th) fluctuation on the gate oxide thickness scaling in 16 nm metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated. Fluctuations of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO(2) for the 1.2 and 0.8 nm EOTs, Al(2)O(3) for the 0.4 nm EOT and HfO(2) for the 0.2 nm EOT) are then for the first time compared with the results of 16 nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property, Result of this study confirms the suppression of V(th) fluctuations with the gate oxide thickness scaling (using high-kappa dielectric). It is found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device's scaling and have potential in the nanoelectronics application. (C) 2008 Elsevier B.V. All rights reserved.
Discrete Dopant Induced Characteristic Fluctuations in 16nm Multiple-Gate SOI Devices
(2007)
Li, Yiming
;
Hwang, Chih-Hong
;
Huang, Hsuan-Ming
;
Yeh, Ta-Ching
;
電信工程研究所
The impact of high-frequency characteristics induced by intrinsic parameter fluctuations in nano-MOSFET device and circuit
(2010-05-01)
Han, Ming-Hung
;
Li, Yiming
;
Hwang, Chih-Hong
;
傳播研究所
;
電機工程學系
This work estimates the influences of the intrinsic parameter fluctuations consisting of metal gate work-function fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits by using an experimentally validated three-dimensional device and coupled device-circuit simulations. The dominance fluctuation source in threshold voltage, gate capacitance, cut-off frequency, high-frequency gain, 3 dB bandwidth, unity-gain bandwidth, power, and the power-added efficiency has been found. Similar to the trend of the cut-off frequency, the PVE and RDF dominate both the device and circuits characteristic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario. (C) 2010 Elsevier Ltd. All rights reserved.
Effect of Single Grain Boundary Position on Surrounding-Gate Polysilicon Thin Film Transistors
(2007)
Li, Yiming
;
Huang, Jung Y.
;
Lee, Bo-Shian
;
Hwang, Chih-Hong
;
電信工程研究所
In this paper, single-grain-boundary-position-induced electrical characteristic variations in 300 nm surrounding-gate (i.e, gate-all-around, GAA) polysilicon thin film transistors (TFTs) are numerically investigated. For a 2T1C active-matrix circuit, a three-dimensional device-circuit coupled mixed-mode simulation shows that the switching speed of GAA TFT can be improved by nine times, compared with the result of the circuit using single-gate (SG) polysilicon TFTs. The position of single grain boundary near the drain side has an ill effect on device performance, but the influence can be suppressed in the GAA polysilicon TFTs. We found that under the same threshold voltage, the variation of threshold voltage can be reduced from 15 % to 5 %, with varying of gate structures of the GAA polysilicon TFT.

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