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Now showing 1 - 10 of 63

Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan
(2013-01-01)
Chen, Wen-Tsuen
;
Lin, Youn-Long
;
Lee, Chen-Yi
;
Chiang, Jeng-Long
;
Chang, Meng-Fan
Taiwan's semiconductor industry has had a profound influence on both domestic economics and the global IT industry. To enhance its competitiveness and expand its global impact, the Taiwan government commenced the National Program for Intelligent Electronics (NPIE) in 2011 to promote technological innovation of medical electronics, green electronics, vehicular (car) electronics, conventional computer, communication, and consumer electronics, the so-called "MG+4C" applications. The government allocated a budget of $430 million over 5 years to facilitate technology development, advanced research, talent cultivation, industry promotion, and international collaboration. By coordinating with government agencies, research institutions, universities, and corporations, the NPIE develops an integrated framework of academia and industry in Taiwan. It also emphasizes the enhancement of product verification, regulations, and participation in international alliances and standards. By transferring academic results to industry in emerging MG+4C applications, it is expected that the NPIE will contribute to the global semiconductor community, energize Taiwan's IC industry, and create innovative products and intelligent systems for better life and better environment.
Architecture of method for fetching microprocessor's instructions
(2002-10-03)
Chen, Pao-Lung
;
Lee, Chen-Yi
A kind of architecture of method for fetching microprocessor's instructions is provided to pre-read and pre-decode a next instruction. If the instruction pre-decoded is found a conditional branch instruction, an instruction reading-amount register is set for reading two instructions next to the current instruction in the program memory, or one is read instead if the next instruction is found an instruction other than the conditional branch one so as to waive reading of unnecessary program memory and thereby reduce power consumption.
Method and apparatus for solving key equation polynomials in decoding error correction codes
(2003-07-03)
Chang, Hsie-Chia
;
Lee, Chen-Yi
The presently invention discloses a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step of the error correction code decoding process whereby the polynomials are generated through at most t intermediate iterations that can be implemented with minimal amount of hardware circuitry. However, depending on the selected (N,K) code, the number of cycles required for the calculation of the polynomials would be within the time required for the calculation of upstream data. Additionally, the present invention for computing the error locator polynomial and the error value polynomial employs an efficient scheduling of a small number of registers and finite-field multipliers (FFMs) without the need of finite-field inverters (FFIs) is illustrated. Using these new methods, a new area-efficient architecture that uses only 4t+2ρ+4 registers and three FFMs and no FFIs is presented to implement the inversionless Euclidean algorithm.
Method for calculating syndrome polynomial in decoding error correction codes
(2003-12-11)
Chang, Hsie-Chia
;
Lee, Chen-Yi
;
Lin, Chien-Ching
The present invention provides a method of calculating the syndrome polynomial in decoding error correction codes. From the relation between the syndromes and the coefficients of the error locator polynomial, the inference that the first t syndromes are zeros, then the next t syndromes are also zeros can be deduced, wherein t is the largest number of correctable errors. For all received codewords, the first t syndromes are calculated. Next, whether the first t syndromes are zeros is judged. If the first t syndromes are zeros, the computation is stopped; otherwise, the next t syndromes are calculated. Therefore, the present invention can judge whether the received codeword is erroneous with only a half of computation, hence effectively reducing the computation in practical operation and achieving the object of low power consumption.
Method and apparatus for solving key equation polynomials in decoding error correction codes
(2003-07-10)
Chang, Hsie-Chia
;
Lee, Chen-Yi
It is an object of the present invention to provide a method and apparatus for solving key equation polynomials in the decoding of codewords. Based upon the Euclidean algorithm, it can be implemented with minimal hardware circuitry and provide a method and apparatus for solving key equation within a t-step iterative decoding procedure while the prior art architectures require at most 2t iterations. It is yet another object of the present invention to provide a method and apparatus for solving key equation polynomials without decreasing the overall decoding speed of the decoder. Briefly, in a presently invention, a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step of the error correction code decoding process is presented whereby the polynomials are generated through at most t intermediate iterations that can be implemented with minimal amount of hardware circuitry. However, depending on the selected (N,K) code, the number of cycles required for the calculation of the polynomials would be within the time required for the calculation of upstream data. Additionally, a presently invention for computing the error locator polynomial and the error value polynomial employs an efficient scheduling of a small number of registers and finite-field multipliers (FFMs) without the need of finite-field inverters (FFIs) is illustrated. Using these new methods, a new area-efficient architecture that uses only 4t+2 ρ+4 registers and three FFMs and no FFIs is presented to implement the inversionless Euclidean algorithm. This method and architecture can be applied to a wide variety of RS and BCH codes with suitable code sizes.
Fast fourier transform processor, dynamic scaling method and fast Fourier transform with radix-8 algorithm
(2005-12-29)
Lee, Chen-Yi
;
Lin, Yu-Wei
The present invention provides a fast Fourier transform processor, dynamic scaling method and fast Fourier transform with radix-8 algorithm. It reduces quantization errors generated from the operation by using a matrix prefetch buffer-based fast Fourier transform processor. Operation sizes of the matrix prefetch buffer as block sizes the invention adjust the signals against overflow by the status of signals in each block. It can shunt time of complex multiplication operation systematically and reduce operation complexity in butterfly units by utilizing algorithms of 3-step radix-8 fast Fourier transform and re-scheduling. Moreover, the present invention provides a fast Fourier transform processor for realizing the methods and algorithms mentioned above.
Transmission method combining trellis coded modulation and low-density parity check code and architecture thereof
(2006-10-19)
Lin, Chien-Ching
;
Chang, Hsie-Chia `
;
Lee, Chen-Yi
The present invention discloses a method combining Trellis Coded Modulation (TCM) and Low-Density Parity Check (LDPC) code and the architecture thereof, which incorporates TCM with LDPC code having better error-correction capability to promote transmission quality and to define TCM of different transmission rates. Further, TCM can utilize less number of states to outperform the conventional spreading so that the hardware complexity in high-speed transmission can be reduced.
Method for updating check-node of low-density parity-check (LDPC) codes decoder and device using the same
(2006-10-26)
Lee, Chen-Yi
;
Lin, Chien-Ching
;
Lin, Kai-Li
;
Chang, Hsie-Chia
The invention provides a method for updating check-node of low-density parity-check (LDPC) codes decoder. The method comprises the following steps: First of all, sort all data that are input into the check-node of LDPC codes decoder to find a minimum absolute value and a second minimum absolute value. Secondly, compare each of all the data to both of the minimum absolute value. If the compared data is equivalent to the current minimum absolute value, the compared data is updated by the secondary minimum absolute value. Otherwise, the compared data is updated by the minimum absolute value.
High-throughput pipelined FFT processor
(2006-12-14)
Lee, Chen-Yi
;
Lin, Yu-Wei
The invention proposes a pipelined FFT processor for UWB system, comprising a first module for implementing radix-2 FFT algorithm; a second module is to realize radix-8 FFT algorithm; a third module is to realize radix-8 FFT algorithm; a plurality of conjugate blocks; a division block; and a plurality of multiplexers. The proposed pipelined FFT architecture called Mixed-Radix Multi-Path Delay Feedback (MRMDF) can provide higher throughput rate by using the multi-data-path scheme. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications.
Dual-mode high throughput de-blocking filter
(2006-11-23)
Lee, Chen-Yi
;
Liu, Tsu-Ming
This invention provides the unique and high-throughput architecture for multiple video standards. Particularly, we propose a novel scheme to integrate the standard in-loop filter and the informative post-loop filter. Due to the non-standardization of post filter, it provides high freedom to develop a certain suitable algorithm for the integration with loop-filter. We modify the post filter algorithm to make a compromise between hardware integration complexity and performance loss. Further, we propose a hybrid scheduling to reduce the processing cycles and improve the system throughput. The main idea is that we use four pixel buffers to keep the intermediate pixel value and perform the horizontal and vertical filtering process in one hybrid scheduling flow. In our approach, we reduce processing cycles, and the synthesized gate counts are very small. Meanwhile, the synthesized results also indicate lower cost for hardware.

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