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A novel 25-nm modified Schottky-barrier FinFET with high performance
(2004-06-01)
Tsui, BY
;
Lin, CP
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
High-performance modified Schottky barrier (MSB) FinFET with 25-nm channel length and fully silicided source/drain (S/D) is proposed for the first time. Using an implant-to-silicide technique, an ultrashort and defect-free S/D extension can be formed at temperature as low as 600 degreesC. The MSB FinFET exhibits better current-voltage characteristics than those of published Schottky barrier devices and FinFETs. With 4-nm-thick gate oxide, the I-on /I-off current ratio higher than 10(9) is achieved. The subthreshold swing of 25-nm and 49-nm MSB FinFETs is 83 and 64.5 mV/dec at room temperature. The advantage of low thermal budget relaxes the thermal stability issue for metal gate/high-kappa dielectric integration. It is believed that the proposed MSB FinFET would be a very promising nano device.
Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET
(2013-10-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
We present a comparative leakage analysis of germanium-on-insulator (GeOI) FinFET and germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit levels. Band-to-band tunneling (BTBT) leakage-induced bipolar effect is found to result in an amplified BTBT leakage for GeOI FinFET. Device and circuit designs to mitigate the amplified BTBT leakage of GeOI FinFETs are suggested. The effectiveness of various high threshold voltage technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed.
Fabrication, characterization and simulation of Omega-gate twin poly-Si FinFET nonvolatile memory
(2013-07-22)
Yeh, Mu-Shih
;
Wu, Yung-Chun
;
Hung, Min-Feng
;
Liu, Kuan-Cheng
;
Jhan, Yi-Ruei
This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Omega-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Omega-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 10(4) program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.
Mobility model extraction for surface roughness of SiGe along (110) and (100) Orientations in HKMG bulk FinFET devices
(2013-09-01)
Chen, Chien-Hung
;
Li, Yiming
;
Chen, Chieh-Yang
;
Chen, Yu-Yu
;
Hsu, Sheng-Chia
In this work, the FinFET HKMG MOS devices are fabricated on silicon wafer with p-substrate. The interface roughness between the SiGe and SiO2 is experimentally extracted and calculated as a function of root mean square by analysis of high resolution transmission electron microscopy. The surface-roughness dependent mobility model is then incorporated into device simulation to study the mobility of SiGe along (110) and (100) orientations of the devices. We further analyze four devices with different surface roughness along (100) and (100) orientations to demonstrate the influence of surface roughness on the total effective mobility. (C) 2013 Elsevier B.V. All rights reserved.
Device and Circuit Performance Estimation of Junctionless Bulk FinFETs
(2013-06-01)
Han, Ming-Hung
;
Chang, Chun-Yen
;
Chen, Hung-Bin
;
Cheng, Ya-Chi
;
Wu, Yung-Chun
The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (V-th) roll-off characteristics at supply voltage (V-DD) 1 V. Analyses of electron density and electric field distributions in ON-state and OFF-state also show that the JL devices have better ON-OFF current ratios. Regarding design aspects, the effects of channel doping concentration (N-ch) and Fin height (H)/width (W) on device V-th are also compared. In addition, the V-th of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (N-sub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (t(HL)) and low-to-high delay time (t(LH)) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.
Investigation and Comparison of Work Function Variation for FinFET and UTB SOI Devices Using a Voronoi Approach
(2013-04-01)
Chou, Shao-Heng
;
Fan, Ming-Long
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Using a novel Voronoi method that can provide a more realistic representation of metal-gate granularity, we investigate and compare the impact of work-function variation (WFV) on FinFET and ultrathin body (UTB) silicon-on-insulator (SOI) devices. Our study indicates that, for a given electrostatic integrity and total effective gate area, the FinFET device exhibits better immunity to WFV than its UTB SOI counterpart. We further show that, unlike other sources of random variation, the WFV cannot be suppressed by equivalent oxide thickness scaling.
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs
(2012-07-01)
Hsieh, Chien-Yu
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-gate 6 T cell, the proposed IG_ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM at V-CS = 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations (L-eff, EOT, W-fin, and H-fin) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of mu/sigma ratio.
A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication
(2011-11-01)
Chen, Hou-Yu
;
Chen, Chun-Chi
;
Hsueh, Fu-Kuo
;
Liu, Jan-Tsai
;
Shy, Shyi-Long
For more than 45 years, photon-and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection lithography (NInL) technique that employs electron-beam-assisted deposition to form pattern-transfer hard mask in a direct-write deposit approach. By scanning the 4.6-nm-diameter electron beam while injecting a suitable organometallic precursor gas around the location of e-beam and just above the substrate, we form a high-density (pitch: 40 nm) high-uniformity (3-sigma linewidth roughness: 2 nm) hard mask for subsequent etching without using proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. The NInL approach simplifies the hard-mask creation or even metal or dielectric pattern creation process modules from five or tens of steps to only a single step. Therefore, it saves both photomask making and wafer processing costs. In addition, room-temperature NInL deposition of conductor/dielectric materials enables the fabrication of small versatile devices and circuits. For demonstration, we fabricated a functional 16-nm six-transistor static random access memory (SRAM) cell (area: occupying only 0.039 mu m(2)), 43% the size of the smallest previously reported SRAM cell, using the FinFET structure and a dynamic V(dd) regulator approach. The NInL technique offers a new way of exploring low-volume high-value 16-nm complementary metal-oxide-semiconductor (CMOS) devices and circuit designs with minimal additional investment and obtains early access to extreme CMOS scaling.
Hot-carrier effects in p-channel modified Schottky-barrier FinFETs
(2005-06-01)
Lin, CP
;
Tsui, BY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
High-performance p-channel modified Schottky-barrier SOI FinFETs (MSB pFinFETs) with low temperature source/drain annealing process was recently suggested for future nano-scale devices. In this letter, the hot-carrier (HC) immunity of the MSB pFinFETs with different gate lengths (L-g) and fin widths (W-f) are presented. The experimental data shows that the MSB pFinFET with narrower W-f has less hot carrier degradation than that with wider W-f. The effects of electrical field in Si fins induced from lateral-gate electrode and the degree of uniformity of source/drain extension are illustrated cautiously by two-dimensional simulation and transmission electron microscopy (TEM) micrographs, respectively. It is found that the devices with narrower W-f have weaker electrical field from gate electrode and better uniformity of source/drain extension resulting in superior hot-carrier immunity. The projected operation voltage at ten years dc lifetime exceeds 1.6 V as the W-f is narrower than 60 nm. It is thus concluded that the MSB pFinFET would be a very promising nano device.
Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs
(2005-11-01)
Tsui, BY
;
Lin, CP
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel modified Schottky barrier p-channel FinFET (MSB FinFET) has been successfully demonstrated previously. In this paper, the detailed process conditions, especially the formation of MSB junctions, has been presented. Device characteristics as well as the geometry effect are also discussed extensively. In the MSB FinFETs fabricated by the two-step silicidation and implant-to-silicide techniques (ITS), an ultrashort and defect-free source/drain extension (SDE) could be formed at a temperature as low as 600 degrees C, resulting in excellent electrical characteristics. The ultrashort SDE could effectively thin out the SB width between source/channel during on-state or broaden and elevate it between drain/channel during off-state. A leakage mechanism of MSB FinFETs similar to the conventional ones was identified by the activation energy analysis. Strong fin width dependence of the electrical characteristics was also found in the proposed devices. When the fin width becomes larger than the silicide grain size, the multigrain structure results in a rough front edge of the MSB junction, which in turn degrades the short-channel device performance. This result indicates that the MSB device is suitable for use as FinFET. The low thermal budget of the MSB FinFET relaxes the thermal stability issue for metal gate/high-k, dielectric integration. It is considered that the proposed MSB FinFET is a very promising nanodevice.

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