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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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🏛️國立陽明交通大學機構典藏

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無線寬頻分碼多工用戶接收器低功率晶片設計
(2001)
張？榮
;
交通大學電信工程系
第十二屆超大型積體電路設計暨計算機輔助設計技術研討會
(2001)
李鎮宜
;
LEE CHEN-YI
;
國立交通大學電子工程學系
超大型積體電路之測試與可測試設計
(1999)
李崇仁
;
交通大學電子工程系
深次微米MOSFET穿隧漏電流、鎖定及靜電放電之研究(II)
(2000)
陳明哲
;
CHEN MING-JER
;
交通大學電子工程研究所
An approach to designing modular extensible linear arrays for regular algorithms
(1998-02-01)
Chang, PY
;
Tsay, JC
;
工學院
;
College of Engineering
The purpose of this paper is to describe a new method to design unidirectional modular extensible linear arrays far regular algorithms. The time complexity of our method is polynomial and depends only on the number of dimensions of the regular algorithm. The designed linear array is asymptotically optimal in space and time.
Power-oriented partial-scan design approach
(1998-08-01)
Jou, JY
;
Nien, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Power consumption and testability are two of major considerations in modern VLSI design. A full-scan method had been used widely in the past, to improve the testability of sequential circuits. Owing to the lower overheads incurred, the partial-scan design has gradually become popular. The authors propose a partial-scan selection strategy which is based on the structural analysis approach and considers the area and power overheads simultaneously. A powerful sample-and-search algorithm is used to find the solution that minimises the user-specified cost function in terms of power and area overheads. The experimental results show that the sample-and-search algorithm derived by the authors can effectively find the best solution of the specified cost function, for almost all circuits, and, on average, the saving of overheads for each specific cost function is significant.
An improved BJT-based silicon retina with tunable image smoothing capability
(1999-06-01)
Wu, CY
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An improved bipolar junction transistor (BJT) based silicon retina with simple and compact structure is proposed and analyzed, In the proposed structure, the BJT smoothing network, which models the layer of horizontal cells in the vertebrate retina, is implemented by placing enhancement n-channel MOSFET's among the bases of parasitic BJT's existing in a CMOS process to form an unique and compact structure. Thus, the smoothing characteristics can be tuned in a wide range. Moreover, an extra emitter is incorporated with each BJT at the pixel to act as the row switch. This reduces the cell area of the silicon retina and increases the resolution. Using the proposed new structure, an experimental 64 x 64 BJT-based silicon retina chip has been fabricated by using 0.5-mu m CMOS technology. The measurement results on the tunability of the smooth area in the smoothing network as well as the dynamic characteristics of the proposed silicon retina in detecting moving objects have been presented. It is believed that the improved structure is very suitable for the very large scale integration implementation of the retina and its application systems for CMOS smart sensors.
Analysis of application of the IDDQ technique to the deep sub-micron VLSI testing
(2002-02-01)
Lu, CW
;
Lee, CL
;
Su, CC
;
Chen, JE
;
電子工程學系及電子研究所
In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 x 10(7) gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.
An efficient VLSI implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters
(2003-09-01)
Wu, BF
;
Hu, YQ
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This work presents a VLSI design rule, namely, an embedded instruction code (EIC), for the discrete wavelet transform (DWT). Our approach derives from the essential computations of DWT, and we establish a set of multiplication instructions, MUL,, and the addition instruction, ADD. In addition, we propose a parallel arithmetic logic unit (PALU) with two multipliers and four adders, called 2M4A. With these requirements, the DWT computation paths can be calculated more efficiently with limited PALUs. Furthermore, since the EIC is operated under the PALU, the number of needed inner registers depends on the wavelet filters' length. Besides, the boundary problem of DWT has also been resolved by the symmetric extension. Moreover, the two-dimensional inverse DWT (2-D IDWT) can be completed using the same PALU for 2-D DWT; the only changes needed to be made are the instruction codes and coefficients. Our chip supports up to six levels of decomposition and versatile image specifications, e.g., VGA, MPEG-1, MPEG-2 and 1024 x 1024 image sizes.
A low-photocuffent CMOS retinal focal-plane sensor with a pseudo-BJT smoothing network and an adaptive current Schmitt trigger for scanner applications
(2004-08-01)
Wu, CY
;
Chiang, CT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, a new structure of low-photocurrent CMOS retinal focal-plane sensor with pseudo-BJT smoothing network and adaptive current Schmitt trigger is proposed. The proposed structure is very simple and compact. This new circuit can easily be implemented in CMOS technology with a small chip area. Another innovation of this circuit is that the proposed circuit could be operated for low-induced current levels (pA), and the current hysteresis of the proposed current Schmitt trigger could be adjusted adaptively according to the value of induced photocurrents. In this work, the detection of static and moving objects, such as a moving white bar, are proven by projecting a pattern through HSPICE simulation. The proposed retinal focal-plane sensor includes a 32 x 32 pixel array with a pixel size of 70 x 70 mum(2). The fill factor is 75% and the total chip area is 3000 x 3030 mum(2). It is with fully functional 32 x 32 implementations consuming less than 8.8 muW per pixel at 3.3 V. Measurement results show that the proposed new retinal focal-plane sensor has successfully been used in character recognition of scanner systems, such as pen scanners, etc.

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🏛️國立陽明交通大學機構典藏

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