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Nitric Acid Oxidized ZrO2 as the Tunneling Oxide of Cobalt Silicide Nanocrystal Memory Devices
(2011-09-01)
Hu, Chih-Wei
;
Chang, Ting-Chang
;
Tu, Chun-Hao
;
Chen, Yang-Dong
;
Lin, Chao-Cheng
In this study, ZrO2 formed by the nitric acid oxidation method is proposed to be the tunneling oxide for nonvolatile memory device applications. The sputtered Zr thin film was oxidized by immersing in the nitric acid solution (HNO3:H2O = 1:10) for 60 s at room temperature. The quality of the formed ZrO2 was also extracted by the capacitance-voltage and current density-voltage measurements. Then, X-ray photoelectron spectroscopy has been used to confirm that the deposited Zr can be oxidized completely after the oxidation process. Moreover, a CoSi2 thin film was deposited on the nitric acid oxidized ZrO2 as the self-assembled layer of the memory device. After the device fabrication, the electrical and material characteristics of the CoSi2 nanocrystal memory devices have also been demonstrated and discussed.
Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation
(2010-12-01)
Chen, Te-Chih
;
Chang, Ting-Chang
;
Chen, Shih-Ching
;
Hsieh, Tien-Yu
;
Jian, Fu-Yen
This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon structure under OFF-state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant ON-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I-V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point.
Charge Quantity Influence on Resistance Switching Characteristic During Forming Process
(2013-04-01)
Chu, Tian-Jian
;
Chang, Ting-Chang
;
Tsai, Tsung-Ming
;
Wu, Hsing-Hua
;
Chen, Jung-Hui
In this letter, we presented that the charge quantity is the critical factor for forming process. Forming is a pivotal process in resistance random access memory to activate the resistance switching behavior. However, overforming would lead to device damage. In general, the overshoot current has been considered as a degradation reason during the forming process. In this letter, the quantity of charge through the switching layer has been proven as the key element in the formation of the conduction path. Ultrafast pulse forming can form a discontinuous conduction path to reduce the operation power.
On-Current Decrease After Erasing Operation in the Nonvolatile Memory Device With LDD Structure
(2011-08-01)
Chang, Geng-Wei
;
Chang, Ting-Chang
;
Syu, Yong-En
;
Tai, Ya-Hsiang
;
Jian, Fu-Yen
The on-current decrease phenomenon is observed after erasing operation in the silicon-oxide-nitride-oxide-silicon thin-film transistors (TFTs) with lightly doped drain (LDD) structure. As nonvolatile memory, when the TFT is programmed again, the on-current decrease phenomenon can be recovered. The on-current decrease and recovery are explained by the energy band diagrams at different drain biases. The explanation implies that this phenomenon only appears in the device with LDD structure, but not in the device without LDD structure, which is experimentally verified.
A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory
(2007-09-01)
Chen, Shih-Ching
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Wu, Yung-Chun
;
Lin, Po-Shun
In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (V-th), and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.
Formation of germanium nanocrystals by rapid thermal oxidizing SiGeO layer for nonvolatile memory application
(2007-12-15)
Chen, Wei-Ren
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Tu, Chun-Hao
;
Yeh, Jui-Lung
A new method to fabricate Ge nanocrystals by rapid thermal oxidizing SiGeO layer for nonvolatile memory application was investigated in this study. The oxidation process nucleated the Ge nanocrystals embedded in the dielectric layer was clearly observed by transmission electron microscope analysis. Moreover, an over-oxidation phenomenon for the formation of GeO2 in this work was found at higher temperature oxidation according to the X-ray photoelectron spectroscopy analysis. The obvious memory window was found in the capacitance-voltage hysteresis curve, and the program efficiency of holes was superior to electrons due to the electronic affinity of GeO2 smaller than silicon substrate for a structure of Ge nanocrystals surrounded with GeO2 layer. Furthermore, the Ge nanocrystals surrounded with GeO2 layer structure has good retention time and endurance. (c) 2007 Elsevier B.V All rights reserved.
Fort-nation of stacked nickel-silicide nanocrystals by using a co-mixed target for nonvolatile memory application
(2007-12-15)
Chen, Wei-Ren
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Tu, Chun-Hao
;
Chi, Feng-Weng
The formation of stacked nickel-silicide nanocrystals by using a co-mixed target is proposed in this paper. High resolution transmission electron microscope analysis clearly shows the stacked nanocrystals embedded in the silicon oxide after rapid thermal oxidation. The obvious memory window can be used to define "1" and "0" states at low voltage operation. In addition, the program/erase characteristics have different charge/discharge efficiency due to the effect of stacked structure. Furthermore, good endurance and retention characteristics are exhibited for nonvolatile memory application. Besides, this technology is suitable for the fabrication of current nonvolatile memory and application of low power device. (C) 2007 Elsevier B.V. All rights reserved.
Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure
(2007-12-15)
Chen, Shih-Ching
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Wu, Yung-Chun
;
Lin, Po-Shun
In this work, we study a polycrystalline silicon thin-film transistor (poly-Si TFT) combined with a silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire channels structure for the applications of transistor and nonvolatile memory. The proposed device named with NW SONOS-TFT has superior electrical characteristics of transistor and also can exhibit high program/erase (P/E) efficiency under adequate bias operation. The V-th decreases from 2.45 V to 1.76 V and subthreshold swing reduces from 0.57 V/decade to 0.42 V/decade. The programming V-th shift is improved from 2.2 V to 3.3 V at 14 V for 1 s and the erasing V-th shift is improved from -0.3 V to -1.3 V at -14 V for 1 s. The dramatic improvement can be attributed to the tri-gate structure and corner effect. In addition, the memory device has a promising data retention behavior at 85 degrees C and a 0.8 V memory window after 5 x 10(3) P/E cycles operations. Hence, the NW SONOS-TFT is suitable for application in the future system-on-panel display. (C) 2007 Elsevier B.V. All rights reserved.

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