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Resist-related damage on ultrathin gate oxide during plasma ashing
(1997-02-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chang, TF
;
Chiou, SG
This paper presents an important observation of plasma-induced damage on ultrathin oxides during O-2 plasma ashing by metal ''antenna'' structures with photoresist on top of the electrodes, It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10(4), In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging, This phenomenon is contrary to most previous reports, It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides.
Effects of isolation oxides on undercut formation and electrical characteristics for silicon selective epitaxial growth
(1997-06-01)
Tseng, HC
;
Chang, CY
;
Pan, FM
;
Chen, LP
;
電子工程學系及電子研究所
Three isolation oxide structures have been prepared to study their resistance to the undercut formation during selective epitaxial growth (SEG) processes. The N2O annealed oxide tetraethyoxysilane (TEOS) oxide stacked structure has the best resistance to the undercut formation and exhibits the best electrical characteristics compared to the other two isolation oxide structures prepared in the study, which are a wet oxide and a TEOS oxide. This is ascribed to a smaller interfacial stress between the isolation oxide and the silicon substrate for the stacked structure. The sidewall damage is the predominant factor deteriorating the current-voltage (I-V) characteristics of the N+-P SEG diodes. When treated with a quick HF dip and followed by a low temperature desorption cleaning before the SEG process, the N+-P SEG diode, which has no perceivable undercut, shows satisfactory I-V characteristics.
Direct oxidation of Si1-xGex layers using Vacuum-Ultra-Violet light radiation in oxygen
(1998-02-01)
Chen, LP
;
Chan, YC
;
Chang, SJ
;
Huang, GW
;
Chang, CY
Oxidation of Si1-xGex films has been carried out by direct photo chemical Vapor deposition (direct photo-CVD) directly with activated O-2 induced by Vacuum-Ultra-Violet (VUV) light radiation, The Auger electron spectroscopy profiles show that no Ge-pileup layer at the oxide/Si1-xGex interface is observed after VUV-induced Si1-xGex oxidation process. The X-ray photoelectron spectroscopy analysis of the samples reveals that Si and Ge are oxidized simultaneously in oxidation process and a mixed oxide layer consisting both SiO2 and GeO2 is formed, This might be the reason that Cc pileup effect is eliminated in this study.
Interfacial abruptness in Si/SiGe heteroepitaxy grown by ultrahigh vacuum chemical vapor deposition
(1997-09-01)
Tsai, WC
;
Chang, CY
;
Jung, TG
;
Chang, TC
;
Lin, HC
High-quality Si/Si1-xGex strained-layer superlattices have been grown in the temperature range 525 degrees C-550 degrees C by ultrahigh vacuum chemical vapor deposition. We employed X-ray reflection and high-resolution double-crystal X-ray diffraction measurements to study the dimensional and compositional variations in a Si/Si1-xGex superlattice. From the X-ray reflection results, the interfacial roughness of Si layers on SiGe, and SiGe layers on Si, is 0.1nm for growth at 525 degrees C and 0.2nm for growth at 550 degrees C. A simple model for estimating the interfacial abruptness of Si/Si1-xGex heterojunctions is proposed. In this model, a transition region with a linearly graded Ge composition is assumed to exist at both Si/Si1-xGex interfaces. The Ge composition x of a Si/Si1-xGex superlattice is found to increase with the growth time at a constant gas phase composition. This phenomenon can be explained by this model, and the thickness of the transition region and the transition time can be extracted from these fitting results. The transition thicknesses are found to be about 0.3-0.7nm for growth at 525 degrees C and 1-1.5nm for growth at 550 degrees C.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
Direct oxidation of Si1-xGex layers using Vacuum-Ultra-Violet light radiation in oxygen
(1998-02-01)
Chen, LP
;
Chan, YC
;
Chang, SJ
;
Huang, GW
;
Chang, CY
Oxidation of Si1-xGex films has been carried out by direct photo chemical Vapor deposition (direct photo-CVD) directly with activated O-2 induced by Vacuum-Ultra-Violet (VUV) light radiation, The Auger electron spectroscopy profiles show that no Ge-pileup layer at the oxide/Si1-xGex interface is observed after VUV-induced Si1-xGex oxidation process. The X-ray photoelectron spectroscopy analysis of the samples reveals that Si and Ge are oxidized simultaneously in oxidation process and a mixed oxide layer consisting both SiO2 and GeO2 is formed, This might be the reason that Cc pileup effect is eliminated in this study.
CMOS RFIC: Application to wireless transceiver design
(2000-02-01)
Wen, KA
;
Wuen, WS
;
Huang, GW
;
Chen, LP
;
Chen, KY
There is increasing interest using CMOS circuits for highly integrated high frequency wireless telecommunications systems. This paper reviews recent works in transceiver architectures, circuits and devices technology for CMOS RFIC application. A number of practical problems those must be resolved in CMOS RFIC design are also discussed.
Deposition of polycrystalline Si and SiGe by ultra-high vacuum chemical molecular epitaxy
(2000-07-01)
Chen, KM
;
Huang, HJ
;
Chang, CY
;
Chen, LP
;
Huang, GW
The polycrystalline Si1-xGex (poly-Si1-xGex) films have better properties than poly-Si for device fabrications, such as lower proceeding temperature and process thermal budget. For these reasons, the poly-Si1-xGex films have been utilized for low-temperature thin film transistor fabrications and gate electrodes of metal-oxide-semiconductor transistors. In this work, disilane and germane were used to grow poly-Si1-xGex films at low temperature (<600 degrees C) by the cold-wall type ultrahigh vacuum chemical molecular epitaxy system. The poly-Si1-xGex films were deposited on oxide and nitride surfaces. The Ge fraction x was evaluated from x-ray diffraction and Auger electron spectroscopy. It is observed that the Ge fraction increases with the increase of the GeH4 flow rate. The result is only slightly related to the substrate type. The growth rate increases with the Ge fraction at lower values and then decreases with the Ge fraction in the higher composition range. This implies that the growth mechanism of poly-Si1-xGex films is different from that of epitaxial Si1-xGex on Si. The uniformity of poly-Si1-xGex films depends on the Ge fraction, and it is improved-by the addition of germanium. The result can be explained by the lower activation energy (<0.25 eV) of poly-Si(1-x)G(x), deposition as compared to that of poly-Si (similar to 2.1 eV). From the x-ray diffraction and atomic force microscopy analyses, the crystallinity and surface roughness of films are suitable for device fabrications. (C) 2000 American Vacuum Society. [S0734-2101(00)07704-6].
Study of boron effects on the reaction of Co and Si1-xGex at various temperatures
(2000-07-01)
Huang, HJ
;
Chen, KM
;
Chang, CY
;
Huang, TY
;
Chang, TC
The effects of boron on Co and Si1-xGex interfacial reaction were studied. Undoped and ill situ boron-doped strained Si0.91Ge0.09 and Si0.86Ge0.14 layers prepared at 550 degrees C by an ultrahigh vacuum chemical vapor deposition system were subjected to Co silicidation at various rapid thermal annealing (RTA) temperatures ranging from 500 to 1000 degrees C. The resulting films were characterized by a sheet resistance measurement, Auger electron spectroscopy, x-ray diffractometry (XRD), high resolution x-ray diffractometry, secondary ion mass spectroscopy, scanning electron microscopy, and transmission electron microscopy. Seen from XRD spectroscopy, a Co(Si1-yGey) cubic structure was formed with RTAs ranging from 500 to 700 degrees C. For boron-doped samples, the CoGe fraction in Co(Si1-yGey) was less than that in undoped samples, indicating that baron atoms retarded the incorporation of Ge into the Co(Si1-yGey) ternary phase. It also led to a large Ge pileup at the interface between the Co-rich and silicidation regions. On the other hand, from the high resolution x-ray spectra, the presence of boron led to less relaxation of the strained Si1-xGex lattice. It is the first time that small boron atoms inhibiting the relaxation of the Si1-xGex layer during silicidation was observed. Furthermore, from the sheet resistance measurement, the formation of CoSi2 was found to be slightly retarded in boron-doped samples, due probably to the decrease of Co or Si diffusivities as a result of boron accumulation at the Co/SiGe reaction interface. At temperatures above 800 degrees C, CoSi2 formed and Ge segregated to the silicide boundaries and the upper reaction region was discovered. These phenomena caused by B dopants are explained in detail. (C) 2000 American Vacuum Society. [S0734-2101(00)04604-2].
Effect of coplanar probe pad design on noise figures of 0.35 mu m MOSFETs
(2000-07-20)
Su, CY
;
Chen, LP
;
Chang, SJ
;
Huang, GW
;
Ho, YP
The effects of different coplanar ground-signal-ground (GSG) probe pads on the noise figure characteristics of submicron MOSFETs are presented. Devices with top-level metal as probe pads shielded by grounded bottom-level metal possess the most appropriate probe pad structure for characterising the noise performance of MOSFETs. Equivalent circuits of the probe pads are used to explain the different noise behaviours.

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