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HIGH-VOLTAGE TOLERANT POWER-RAIL ESD CLAMP CIRCUIT
(2007-10-04)
Ker, Ming-Dou
;
Chen, Wen-Yi
A high-voltage tolerant power-rail ESD clamp circuit is proposed, in which circuit devices can safely operate under the high power supply voltage that is three times larger than their process limitation without gate-oxide reliability issue. Moreover, an ESD detection circuit is used to effectively improve the whole ESD protection function by substrate-triggered technique. Because only low voltage (1*VDD) devices are used to achieve the object of high voltage (3*VDD) tolerance, the proposed design provides a cost effective power-rail ESD protection solution to chips with mixed-voltage interfaces.
Preparation and characterization of high-durability zwitterionic crosslinked proton exchange membranes
(2010-10-15)
Ye, Yun-Sheng
;
Chen, Wen-Yi
;
Huang, Yao-Jheng
;
Cheng, Ming-Yao
;
Yen, Ying-Chieh
The present present paper describes the development of a novel proton exchange membrane comprising a poly (styrene sulfonic acid-co-4-vinylpyridine) copolymer that was crosslinked with a haloalkyl crosslinker through the formation of ionic bonding linkages The nucleophilic substitution of these crosslinked membranes as well as a model reaction between pyridine and 1-bromobutane was confirmed by nuclear magnetic resonance (NMR) Tough and flexible membranes of a high mechanical strength were prepared. They demonstrated very elevated thermal, hydrolytic and oxidative stabilities as compared to other sulfonated polymers. The crosslinked membrane composed of zwitterionic molecules with a crosslinking fraction of 90.3, denoted SP-1, exhibited a proton conductivity of ca 7 1 x 10(-2) S cm(-1) at 30 degrees C under 90% relative humidity; a value comparable to that of Nafion 117 Moreover, the crosslinked SP-1 membrane possessed the highest selectivity for methanol fuel cells (3 38 x 10(5) S cm(-3) s), approximately five times that of Nafion 117. thus implying its potential for practical use in high-energy-density devices (C) 2010 Elsevier B.V All rights reserved.
Measurement on Snapback Holding Voltage of High-Voltage LDMOS for Latch-up Consideration
(2008)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
Huang, Yeh-Jen
;
Jou, Yeh-Ning
;
Lin, Geeng-Lih
In high voltage (HV) ICs, the latch-up immunity of HV devices is often referred to the TLP-measured holding voltage because the huge power generated from DC curve tracer can easily damage HV device during measurement. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-mu m 18-V bipolar CMOS DMOS (BCD) process to investigate the validity of TLP-measured snapback holding voltage to the device immunity against latch-up. Experimental results from curve tracer measurement and transient latch-up test show that 100-ns TLP underestimates the latch-up susceptibility of the 18-V LDMOS. By using the long-pulse TLP measurement, snapback holding voltage of the HV device has been found to degrade over time due to the self-heating effect. As a result, since the latch-up event is a reliability test with the time duration longer than millisecond, TLP measurement is not suitable for applying to investigate the snapback holding voltage of HV devices for latch-up.
A BENDING N-WELL BALLAST LAYOUT TO IMPROVE ESD ROBUSTNESS IN FULLY-SILICIDED CMOS TECHNOLOGY
(2010)
Wen, Yong-Ru
;
Ker, Ming-Dou
;
Chen, Wen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Ballast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending N-Well (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS.
ESD Protection Circuit for High-Voltage CMOS ICs with Improved Immunity Against Transient-Induced Latchup
(2010)
Ker, Ming-Dou
;
Hsu, Che-Lun
;
Chen, Wen-Yi
;
電機學院
;
College of Electrical and Computer Engineering
With high normal operating voltages, latchup is an important reliability issue for high-voltage (HV) ICs. Harsh operating environments further deteriorate the transient-induced latchup (TLU) immunity of HV ICs. High immunity against TLU has therefore become an important reliability factor of HV ESD protection circuits. In this work, a novel ESD protection circuit with HV silicon controlled rectifier as the main ESD protection element has been proposed. The new proposed ESD protection circuit has been verified in a 0.5-mu m 16-V Bipolar CMOS DMOS process. Experimental results showed that the new proposed ESD protection circuit has high TLU immunity of +220V/-295V and high human body model (machine model) ESD robustness of 4.5kV (500V) at the same time.
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs
(2011-02-01)
Ker, Ming-Dou
;
Chen, Wen-Yi
;
Shieh, Wuu-Trong
;
Wei, I-Ju
;
電機學院
For integrated circuits (ICs) with voltage programming pin (V(PP) pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the V(PP) pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to V(DD) cannot be applied to such V(PP) pin. In this work, a new ESD protection design is proposed to improve ESD robustness of V(PP) pin with the consideration of the mistriggering issue when V(PP) programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.
Improving Safe Operating Area of nLDMOS Array With Embedded Silicon Controlled Rectifier for ESD Protection in a 24-V BCD Process
(2011-09-01)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In high-voltage technologies, silicon-controlled rectifier (SCR) is usually embedded in output arrays to provide a robust and self-protected capability against electrostatic discharge (ESD). Although the embedded SCR has been proven as an excellent approach to increasing ESD robustness, mistriggering of the embedded SCR during normal circuit operating conditions can bring other application reliability concerns. In particular, the safe operating area (SOA) of output arrays due to SCR insertion has been seldom evaluated. In this paper, the impact of embedding SCR to the electrical SOA (eSOA) of an n-channel LDMOS (nLDMOS) array has been investigated in a 24-V bipolar CMOS-DMOS process. Experimental results showed that the nLDMOS array suffers substantial degradation on eSOA due to embedded SCR. Design approaches, including a new proposed poly-bending (PB) layout, were proposed and verified in this paper to widen the eSOA of the nLDMOS array with embedded SCR. Both the high ESD robustness and the improved SOA of circuit operation can be achieved by the new proposed PB layout in the nLDMOS array.
Characterization of SOA in Time Domain and the Improvement Techniques for Using in High-Voltage Integrated Circuits
(2012-06-01)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Safe operating area (SOA) in power semiconductors is one of the most important factors affecting device reliability. The SOA region of power MOSFETs must be well characterized for using in circuit design to meet the specification of applications, particularly including the time domain of circuit operations. In this paper, the characterization of SOA in the time domain is performed with the experimental measurement on silicon devices, and the useful techniques to improve SOA of power MOSFETs for using in high-voltage integrated circuits are overviewed.
Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection
(2009)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
Jou, Yeh-Ning
;
Huang, Yeh-Jen
;
Lin, Geeng-Lih
With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mu m 16-V BCD process. The TIP measured results confirmed that the secondary breakdown current (I(t2)) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.
Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection
(2012-03-01)
Chen, Wen-Yi
;
Rosenbaum, Elyse
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Diode-triggered silicon-controlled rectifiers(DTSCRs) are used for on-chip electrostatic discharge protection. The role of the trigger diode string in determining the transient voltage overshoot is investigated using a very fast transmission line pulse. A DTSCR containing only poly-bound trigger diodes has a voltage overshoot of just 1.5 V at 7 A, which is significantly less than what is found with STI-bound diodes. A DTSCR with only STI-bound trigger diodes has a lower leakage current. Therefore, DTSCRs with different trigger diode configurations may be suitable for different applications, e. g., high speed or low power.

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