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Item type:Item, RF noise in 0.18-mu m and 0.13-mu m MOSFETs(2002-12-01) ;Huang, CH ;Lai, CH ;Hsieh, JC ;Liu, JChin, AWe have studied the gate finger number and gate ength dependence on minimum noise figure (NFmin) in deep submicrometer MOSFETs. A lowest NFmin. of 0.93 dB is measured in 0.18-mum MOSFET at 5.8 GHz as increasing finger number to 50 fingers, but increases abnormally when above 50. The scaling gate length to 0.13 mum shows larger NFmin than the 0.18-mum case at the same finger number. From the analysis of a well-calibrated device model, the abnormal finger number dependence is due to the combined effect of reducing gate resistance and increasing substrate loss as increasing finger number. The scaling to 0.13-mum MOSFET gives higher NFmin due to the higher gate resistance and a modified T-gate structure proposed to optimize the NFmin for further scaling down of the MOSFET.Item type:Item, Fully silicided NiSi gate on La2O3 MOSFETs(2003-05-01) ;Lin, CY ;Ma, MW ;Chin, A ;Yeo, YCZhu, CXWe have fabricated the fully silicided NiSi on La2O3 for n- and p-MOSFETs. For 900 degreesC fully silicided CoSi2 on La2O3 gate dielectric with 1.5 mn EOT, the, gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gat e leakage current density of 2 x 10(-4) A/cm(2) at 1 V is measured for 400 degreesC formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm(2)/V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO2 MOSFETs without using H-2 annealing.Item type:Item, Fully silicided NiSi and germanided NiGe dual gates on SiO2 n- and p-MOSFETs(2003-12-01) ;Yu, DS ;Wu, CH ;Huang, CH ;Chin, AChen, WJWe have fabricated the fully silicided NiSi and germanided NiGe dual gates n- and p-MOSFETs on 1.9 nm thick SiO2 gate dielectric. The extracted work functions of fully NiSi and NiGe gates from thickness-dependent flat band voltage were 4.55 and 5.2 eV respectively, which may provide possible wide work function tuning using NiSi1-xGex. In additional to the lower gate current than Al gate n- and p-MOSFETs, the fully silicided NiSi and germanided NiGe gates MOSFETs show electron and hole mobilities close to universal mobility values with special advantage of process compatible to current VLSI fabrication line.Item type:Item, Al2O3-Ge-On-insulator n- and p-MOSFETs with fully NiSi and NiGe dual gates(2004-03-01) ;Yu, DS ;Huang, CH ;Chin, A ;Zhu, CXLi, MFHigh-kappa, A1(2)O(3)/Ge-on-insulator (GOI) n- and p-MOSFETs with fully silicided NiSi and germanided NiGe dual gates were fabricated. At 1.7-nm equivalent-oxide-thickness (EOT), the A1(2)O(3)-GOI with metal-like NiSi and NiGe gates has comparable gate leakage current with A1(2)O(3)-Si MOSFETs. Additionally, A1(2) O-3-GOI C-MOSFETs with fully NiSi and NiGe gates show 1.94 and 1.98 times higher electron and hole mobility, respectively, than A1(2)O(3)-Si devices, because the electron and hole effective masses of Ge are lower than those of Si. The process with maximum 500 degreesC rapid thermal annealing (RTA) is ideal for integrating metallic gates with high-kappa to minimize interfacial reactions and crystallization of the high-kappa material, and oxygen penetration in high-kappa MOSFETs.Item type:Item, Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode(2004-05-01) ;Zhu, SY ;Yu, HY ;Whang, SJ ;Chen, JHShen, CThis letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-kappa gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi source/drain (S/D), excellent electrical performance of I-on/I-off similar to 10(7) - 10(8) and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, I-on/I-off can reach similar to 10(5) at V-ds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-kappa dielectric and metal-gate materials to be used in the future generation CMOS technology.Item type:Item, N-type Schottky barrier source/drain MOSFET using ytterbium silicide(2004-08-01) ;Zhu, SY ;Chen, JD ;Li, MF ;Lee, SJSingh, JYtterbium silicide, for the first time, was used to form the Schottky barrier source/drain (S/D) of N-channel MOSFETs. The device fabrication was performed at low temperature, wich is highly preferred in the establishment of Schottky barrier S/D transistor (SSDT) technology, including the HfO2 gate dielectric, and HaN/TaN metal gate. The YbSi2-x, silicided N-SSDT has demonstrated a very promising characteristic with a recorded high I-on/I-off ratio of similar to10(7) and a steep subthreshold slope of 75 mV/dec, which is attributed to the lower electron barrier height and better film morphology of the YbSi2-x/Si contact compared with other self-aligned rare earth metal-(Erbium, Terbium, Dysprosium) silicided Schottky junctions.Item type:Item, A TaN-HfO2-Ge pMOSFET with novel SiH4 surface passivation(2004-09-01) ;Wu, N ;Zhang, QC ;Zhu, CX ;Chan, DSHDu, AYIn this letter, we demonstrate a novel surface passivation process for HfO2 Ge pMOSFETs using SiH4 surface annealing prior to HfO2 deposition. By using SiH4 passivation, a uniform amorphous interfacial layer is formed after device fabrication. Electrical results show that the HfO2 Ge MOSFET with Si-passivation exhibits less frequency dispersion, narrower gate leakage current distribution, and a similar to 140% higher peak mobility than that of the device with surface nitridation.Item type:Item, Germanium pMOSFETs with Schottky-barrier germanide S/D, high-kappa gate dielectric and metal gate(2005-02-01) ;Zhu, SY ;Li, R ;Lee, SJ ;Li, MFDu, AYSchottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as similar to5 times due to the lower hole Schottky barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.Item type:Item, Three-dimensional metal gate-high-kappa-GOI CMOSFETs on 1-poly-6-metal 0.18-mu m Si devices(2005-02-01) ;Yu, DS ;Chin, A ;Liao, CC ;Lee, CFCheng, CFWe demonstrate three-dimensional (3-D) self-aligned [IrO2-IrO2-Hf]-LaAlO3-Ge-on-Insulator (GOI) CMOSFETs above 0.18-mum Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO2-LaAlO3-GOI p-MOSFETs and IrO2-Hf-LaAlO3-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm(2)/Vs respectively, without depredating the underneath 0.18-mum Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.Item type:Item, Low noise and high gain RF MOSFETs on plastic substrates(2005) ;Kao, HL ;Chin, A ;Huang, CC ;Hung, BFChiang, KCA low minimum noise figure (NFmin) of 1.2 dB and high associated gain of 12.8 dB at 10 GHz, were measured for 0.18 mu m RF MOSFETs on plastic, made by substrate thinning (similar to 30 mu m), transfer and bonding. The performance can be further improved to 0.96 dB NFmin and 14.1 dB associated gain at 10 GHz, under applied tensile strain, using flexible Si on plastic. A 3.5 nH inductor on plastic showed a 55% higher Q-factor with a wider frequency range, compared with that on a Si substrate.