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High Performance Metal-Gate/High-kappa GaN MOSFET With Good Reliability for Both Logic and Power Applications
(2016-09-01)
Yi, Shih-Han
;
Ruan, Dun-Bao
;
Di, Shaoyan
;
Liu, Xiaoyan
;
Wu, Yung Hsien
The gate-recessed GaN MOSFET on a Si substrate is demonstrated to achieve a record highest normalized transistor current (mu C-ox) of 335 mu A/V-2 (410 mA/mm at L-G = 5 mu m and only V-G = 4 V), I-ON/I-OFF of 9 orders of magnitude, small 79 mV/dec sub-threshold slope, a low oxide/GaN interface trap density of 1.2 x 10(10) eV(-1)/cm(2), a low on-resistance of 17.0 Omega-mm, a high breakdown voltage of 720-970 V, and excellent reliability of only 40 mV Delta V-T after 175 degrees C 1000 s stress at maximum drive current. Such excellent device integrities are due to the high-kappa gate dielectric and the high conduction band offset (Delta E-C) of SiO2/GaN. From the calculation results of self-consistent Schrodinger and Poisson equations, the good reliability of GaN MOSFET is related to the confined carrier density within the GaN channel, which is in sharp contrast to the strong wave-function penetration into the high-trap density AlGaN barrier in the AlGaN/GaN HEMT.
Very low noise in 90nm node RF MOSFETs using a new layout
(2007-01-01)
Kao, H. L.
;
Chin, Albert
;
Liao, C. C.
;
McAlister, S. P.
;
電子工程學系及電子研究所
We have directly measured a record low minimum noise figure (NFmin) of 0.46 dB at 10 GM, along with a high 16.6 dB Associated Gain, in an 8-finger 90 nm node MOSFET (L-G = 65nm) without de-embedding. At 18 GHz, NFmin was 0.83 dB with 13.5 dB gain. This was achieved using a microstrip line layout to screen the RF noise generated by the lossy substrate.
High-Performance GaN MOSFET With High-k LaAlO3/SiO2 Gate Dielectric
(2012-01-01)
Tsai, C. Y.
;
Wu, T. L.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Using a high-k LaAlO3/SiO2 gate dielectric, the recessed-gate GaN MOSFET has a low threshold voltage (V-t) of 0.1 V, low on-resistance (R-on) of 13.5 Omega . mm, high breakdown voltage of 385 V, high transconductance (g(m)) of 136 mS/mm, and record-best normalized drive current (mu C-ox) of 172 mu A/V-2. Such excellent device integrity is due to the small capacitance equivalent thickness of 3.0 nm, using a high-k gate dielectric and recessed-gate etching.
PBTI Investigation of MoS2 n-MOSFET With Al2O3 Gate Dielectric
(2017-05-01)
Yuan, Hui-Wen
;
Shen, Hui
;
Li, Jun-Jie
;
Shao, Jinhai
;
Huang, Daming
For the first time, we report the positive bias temperature instability of the back gated multilayer MoS2 n-MOSFETs with Al2O3 gate dielectric. In the stress phase, the Id-Vg curve shifts to the positive gate bias. In the recovery phase, it shifts back to the negative gate bias. After 5000 s recovery, it completely recovers to that of the fresh device. The results indicate that the voltage shift is solely due to trapping and detrapping of the pre-existing border traps in the Al2O3 dielectric. The traps consist of fast and slow components with the capture time constants of 7 and 1.8 x 10(2) s and the emission time constants of 15 and 1.0 x 10(3) s, respectively. The results from first-order trapping and detrapping calculations are in overall agreements with 12 measured Delta Vg curves including six under stress voltages and six in the recovery phases. The energy densities for the fast and slow traps are derived to be in the order of 10(13) cm(- 2) eV(-1) above the bottom of the MoS2 conduction band.
Investigation of Traps at MoS2/Al2O3 Interface in nMOSFETs by Low-Frequency Noise
(2016-04)
Yuan, Hui-Wen
;
Shen, Hui
;
Li, Jun-Jie
;
Shao, Jinhai
;
Huang, Daming
A new method is proposed to distinguish the contributions of the low-frequency noise (LFN) from the channel and the source/drain Schottky contacts in MOS devices. The method is applied to back-gated nMOSFETs with MoS2 channel and Al2O3 gate dielectric. To avoid a possible noise signal contamination from the top MoS2 surface by oxygen or water molecules absorption, the nMOSFETs with multilayer MoS2 are fabricated, and the measurements are carried out in the vacuum. The trap density Not at the MoS2/Al2O3 interface is derived for the first time using the proposed method. It is found that the Not responsible to LFN depends strongly on the surface potential, ranging from 4 x 10(10) cm(-2) in the weak over-drive region to 5 x 10(11) cm(-2) in the strong over-drive region.
High Performance RF Passive Devices and Noise-Shielding MOSFET on IC-Standard Si Wafer for Sub-THz Applications
(2013)
Chin, Albert
;
Kao, Hsuan-Ling
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The operation frequency of a MOSFET is approaching THz as continuously scaling down into 1X nm. Nevertheless, the very high power loss of transmission line on IC-Standard Si wafer (similar to 5 dB/mm at 110 GHz) is the fundamental limitation for Si-based sub-THz IC. Using a simple method to translate standard 10 Omega-cm low resistivity into semi-insulating, very low loss transmission line and broad filters have been realized on Si wafer to 110 GHz, with performance near ideal devices by EM design. The noise coupling of CPW-layout RF MOSFET can also be filtered using a microstrip line design, and a low min. noise figure (NFmin) of 0.5 dB at 10 GHz was measured in a 90 nm MOSFET.
Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric
(2014-01-01)
Cheng, Chun-Hu
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The power consumption of capacitor leakage current, increase of the capacitor aspect ratio, and lack of higher dielectric constant (kappa) material are the difficult challenges to downscaling dynamic random access memory (DRAM). This letter reports a new one-transistor ferroelectric-MOSFET (1T FeMOS) device that displays DRAM functions of a 5 ns switching time, 10(12) on/off endurance cycles, and 30 times on/off retention windows at 5 s and 85 degrees C. A simple 1T process and a considerably low OFF-state leakage of 3 x 10(-12) A/mu m were achieved. This novel device was achieved by applying ferroelectric ZrHfO gate dielectric to a p-MOSFET, which is fully compatible with existing high-kappa CMOS processing.
DC-RF performance improvement for strained 0.13 mu m MOSFETs mounted on a flexible plastic substrate
(2006)
Kao, H. L.
;
Chin, Albert
;
Liao, C. C.
;
Tseng, Y. Y.
;
McAlister, S. P.
By applying 0.7% tensile strain to the flexible die of a 0.13 mu m thin-body (40 mu m) Si MOSFET mounted on plastic, both the DC and RF performance have been improved. The current I(d,sat) was 14.3% higher, and f(T) increased from 103 to 118 GHz with NF(min) decreasing from 0.89 to 0.75 dB at 10 GHz. These improvements are comparable with those for SiN-capped 90 nm strained-Si nMOS and consistent with device simulations. The approach has the advantages of better RF passive devices on the insulating plastic substrate and low cost.
High-temperature stable HfLaON p-MOSFETs with high-work-function Ir3Si gate
(2007-04-01)
Wu, C. H.
;
Hung, B. F.
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Chin, Albert
;
Wang, S. J.
;
Wang, X. P.
We report a novel 1000 degrees C stable HfLaON p-MOSFET with Ir3Si gate. Low leakage current of 1.8 x 10(-5) A/cm(2) at 1 V above flat-band voltage, good effective work function of 5.08 eV, and high mobility of 84 cm(2)/V center dot s are simultaneously obtained at 1.6 nm equivalent oxide thickness. This gate-first p-MOSFET process with self-aligned ion implant and 1000 degrees C rapid thermal annealing is fully compatible to current very large scale integration fabrication lines.
Work function tunability of refractory metal nitrides by lanthanum or aluminum doping for advanced CMOS devices
(2007-11-01)
Wang, Xin Peng
;
Lim, Andy Eu-Jin
;
Yu, Hong Yu
;
Li, Ming-Fu
;
Ren, Chi
A lanthanum (La)-doped HfN is investigated as an n-type metal gate electrode on SiO(2) with tunable work function. The variation of La concentration in (Hf(x)La(1-x))N(y) modulates the gate work function from 4.6 to 3.9 eV and remains stable after high-temperature annealing (900 degrees C to 1000 degrees C, which makes it suitable for n-channel MOSFET application. An ultrathin high-k dielectric layer was formed at the metal/SiO(2) interface due to the (Hf(x)La(1-x))N(y) and SiO(2) interaction during annealing. This causes a slight reduction in the effective oxide thickness and improves the tunneling current of the gate dielectric by two to three orders. We also report the tunability of TaN with Al doping, which is suitable for a p-type metal gate work function. Based on our results, several dual-gate integration processes by incorporating lanthanum or aluminum into a refractory metal nitride for CMOS technology are proposed.

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