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High Performance Metal-Gate/High-kappa GaN MOSFET With Good Reliability for Both Logic and Power Applications
(2016-09-01)
Yi, Shih-Han
;
Ruan, Dun-Bao
;
Di, Shaoyan
;
Liu, Xiaoyan
;
Wu, Yung Hsien
The gate-recessed GaN MOSFET on a Si substrate is demonstrated to achieve a record highest normalized transistor current (mu C-ox) of 335 mu A/V-2 (410 mA/mm at L-G = 5 mu m and only V-G = 4 V), I-ON/I-OFF of 9 orders of magnitude, small 79 mV/dec sub-threshold slope, a low oxide/GaN interface trap density of 1.2 x 10(10) eV(-1)/cm(2), a low on-resistance of 17.0 Omega-mm, a high breakdown voltage of 720-970 V, and excellent reliability of only 40 mV Delta V-T after 175 degrees C 1000 s stress at maximum drive current. Such excellent device integrities are due to the high-kappa gate dielectric and the high conduction band offset (Delta E-C) of SiO2/GaN. From the calculation results of self-consistent Schrodinger and Poisson equations, the good reliability of GaN MOSFET is related to the confined carrier density within the GaN channel, which is in sharp contrast to the strong wave-function penetration into the high-trap density AlGaN barrier in the AlGaN/GaN HEMT.
High-Performance Gate-First Epitaxial Ge n-MOSFETs on Si With LaAlO3 Gate Dielectrics
(2010-12-01)
Chen, W. B.
;
Cheng, C. H.
;
Chin, Albert
;
光電學院
;
電子工程學系及電子研究所
This brief presents high-performance Ge n-MOSFETs with good high-field mobility of 218 cm(2)/V . s at 0.5 MV/cm, low subthreshold swing (SS) of 108 mV/dec, small equivalent oxide thickness (EOT) of 1.6 nm, low 7 x 10(-10) A/mu m OFF-state leakage, small bias temperature instability of 31 mV at 1.2 V overdrive and 85 degrees C, and full process compatibility with current very large-scale integration fabrication. These are one of the best SS and high-field mobility data among gate-first Ge n-MOSFETs using epitaxial Ge on 6-in Si wafer and proper high-kappa LaAlO3 dielectric without using an interfacial layer. Using a different high-kappa HfAlO gate dielectric, the Ge n-MOSFETs showed poor leakage, large flatband voltage shift, and degraded EOT.
Ultra-Low Power Green Electronic Devices
(2015)
Yi, S. H.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Power consumption is the crucial challenge for electronics. To lower the DC leakage power (P-DC), we applied the high-kappa gate dielectric to CMOS from the physics of Q equivalent to CV. More than 2 orders of magnitude lower P-DC is obtained at small 0.5 similar to 0.9 nm equivalent-oxide-thickness (EOT). The high-kappa dielectric also increases the charge controllability of flash memory and decrease the V-T disturbance by nearly cells, which improves cell density and cost. The AC power (P-AC) can be lowered by using high-mobility Ge CMOS at a lower V-D and 3D IC with a small capacitance, from basic physics of P-AC equivalent to CV(D)(2)f/2.
Metal-Gate/High-kappa/Ge nMOS at Small CET With Higher Mobility Than SiO2/Si at Wide Range Carrier Densities
(2013-02-01)
Liao, C. C.
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Ku, T. C.
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Lin, M. H.
;
Zeng, Lang
;
Kang, Jinfeng
High-performance TaN/TiLaO/La2O3/SiO2/(111)-Ge nMOSFETs show high mobility of 432 cm(2)/V . s at 10(13) cm(-2) carrier density (N-s), good 1.05 junction ideality factor, and small subthreshold swing of 101 mV/dec, at a small 1.1-nm capacitance-equivalent thickness (CET). This is the first report of higher mobility in the Ge nMOSFET than SiO2/Si universal mobility at wide medium-high N-s range and small CET of 1.1 nm, which is attributed to using the (111)-Ge substrate, 30-ns laser annealing, SiO2 interfacial layer, and YbGex/n-Ge contact.
Improved high-temperature leakage in high-density MIM capacitors by using a TiLaO dielectric and an Ir electrode
(2007-12-01)
Cheng, C. H.
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Pan, H. C.
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Yang, H. J.
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Hsiao, C. N.
;
Chou, C. P.
We have fabricated high-kappa. TaN/Ir/TiLaO/TaN metal-insulator-metal capacitors. A low leakage current of 6.6 x 10(-7) A/cm(2) was obtained at 125 degrees C for 24-fF/mu m(2) density capacitors. The excellent device performance is due to the combined effects of the high-kappa TiLaO dielectric, a high work-function Ir electrode, and large conduction band offset.
Low subthreshold swing HfLaO/pentacene organic thin-film transistors
(2008-03-01)
Chang, M. R.
;
Lee, P. T.
;
McAlister, S. P.
;
Chin, Albert
;
電子工程學系及電子研究所
We have integrated a high-kappa HfLaO dielectric into pentacene-based organic thin-film transistors. We measured good device performance, such as a low subthreshold swing of 0.078 V/dec, a threshold voltage of - 1.3 V, and a field-effect mobility of 0.71 cm(2)/V.s. This occurred along with an ON-OFF state drive current ratio of 1.0 x 10(5), when the devices were operated at only 2 V. The performance is due to the high gate-capacitance density of 950 nF/cm(2) that is given by the HftaO dielectric, which is achieved at an equivalent oxide thickness of only 3.6 nm with a low leakage current of 5.1 x 10(-7) A/cm(2) at 2 V.
Higher Gate Capacitance Ge n-MOSFETs Using Laser Annealing
(2011-04-01)
Chen, W. B.
;
Shie, B. S.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
By applying laser annealing (LA) on both gate dielectrics and source/drain activation, the TaN/ZrO(2)/La(2)O(3)/SiO(2) on Ge n-MOSFETs shows a high gate capacitance density, a small n(+)/p-junction ideality factor of 1.10, a small subthreshold swing (SS) of 106 mV/dec, and a good high-field mobility of 285 or 340 cm(2)/V . s after gate leakage correction at 1 MV/cm, at a small 0.95-nm equivalent oxide thickness (EOT). To the best of our knowledge, this is the first demonstration of significantly high gate capacitance in MOSFETs by LA. This is also the highest 1-MV/cm mobility at the smallest EOT of Ge n-MOSFETs and better than the SiO(2)/Si universal mobility.
Comparison of MONOS memory device integrity when using Hf(1-x-y)N(x)O(y) trapping layers with different N compositions
(2008-06-01)
Yang, H. J.
;
Cheng, C. F.
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Chen, W. B.
;
Lin, S. H.
;
Yeh, F. S.
We have studied the nitrogen composition dependence of the characteristics of TaN/HfLaON/Hf(1-x-y)N(x)O(y)/ SiO(2)/Si MONOS memory devices. By increasing the N composition in the Hf(1-x-y)N(x)O(y) trapping layer, both the memory window And high-temperature retention improved. The Hf(0.3)N(0.2)O(0.5) MONOS device displayed good characteristics in terms of its +/-9-V program/erase (P/E) voltage, 100-mu s P/E speed, large initial 2.8-V memory window, and a ten-year extrapolated retention of 1.8 V at 85 degrees C or 1.5 V at 125 degrees C.
Improving the retention and endurance characteristics of charge-trapping memory by using double quantum barriers
(2008-07-01)
Lin, S. H.
;
Yang, H. J.
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Chen, W. B.
;
Yeh, F. S.
;
McAlister, Sean P.
We have studied the performance of double-quantum-barrier [TaN - Ir(3)Si] - [HfAlO - LaAlO(3)] - Hf(0.3)N(0.2)O(0.5) - [HfAlO - SiO(2)]-Si charge-trapping memory devices. These devices display good characteristics in terms of their +/- 9-V program/erase (P/E) voltage, 100-mu s P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 degrees C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced-interface trap generation.
Small-Subthreshold-Swing and Low-Voltage Flexible Organic Thin-Film Transistors Which Use HfLaO as the Gate Dielectric
(2009-02-01)
Chang, M. F.
;
Lee, P. T.
;
McAlister, S. P.
;
Chin, Albert
;
電子工程學系及電子研究所
Pentacene organic thin-film transistors (OTFTs) with a high-k HfLaO dielectric were integrated onto flexible polyimide substrates. The pentacene OTFTs exhibited good performance, such as a low subthreshold swing of 0.13 V/decade and a threshold voltage of -1.25 V. The field-effect mobility was 0.13 cm(2)/V . s at an operating voltage as low as only 2.5 V. These characteristics are attractive for high-switching-speed and low-power applications.

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