學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Search Results

Now showing 1 - 10 of 24

ESD Protection Design for Wideband RF Applications in 65-nm CMOS Process
(2014)
Chu, Li-Wei
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
;
Tseng, Jen-Chou
All wireless communication products must meet the reliability specifications during mass production. To prevent from electrostatic discharge (ESD) damages, the ESD protection designs must be added at all input/output pads in chip. Some ESD protection designs with low parasitic capacitance for radio-frequency (RF) applications are reviewed in this paper. Besides, a novel ESD protection design is proposed and realized in a 65nm CMOS process to protect the wideband RF circuits. In this work, diodes are used for ESD protection and inductors are used for high-frequency performance fine tuning. Experimental results of the test circuits have been successfully verified.
Improving ESD Robustness of Stacked Diodes with Embedded SCR for RF Applications in 65-nm CMOS
(2014)
Lin, Chun-Yu
;
Fan, Mei-Lian
;
Ker, Ming-Dou
;
Chu, Li-Wei
;
Tseng, Jen-Chou
To protect the radio-frequency (RF) integrated circuits from the electrostatic discharge (ESD) damage in nanoscale CMOS process, the ESD protection circuit must be carefully designed. In this work, stacked diodes with embedded silicon-controlled rectifier (SCR) to improve ESD robustness was proposed for RF applications. Experimental results in 65-nm CMOS process show that the proposed design can achieve low parasitic capacitance, low turn-on resistance, and high ESD robustness.
Novel Shift Register Using Amorphous Silicon TFTs for Liquid Crystal Displays Application
(2011)
Chu, Li-Wei
;
Yang, Meng-Chuan
;
Liu, Po-Tsun
;
Kuo, Yi-Chun
;
光電工程學系
A new shift register has been successfully designed and integrated for a 3.8-inch WVGA (800xRGBx480) panel. With the proposed threshold voltage drop cancellation technique, output rise time can be substantially decreased by 24.6% for high resolution display application. Furthermore, the demonstrated panel shows almost no degradation after 500 hours operation.
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
(2014-12-01)
Lien, Nan-Chun
;
Chu, Li-Wei
;
Chen, Chien-Hen
;
Yang, Hao-I.
;
Tu, Ming-Hsien
This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. The design employs boosted word-line (WL) for improving both read performance and write-ability. A ripple bit-line (RiBL) structure provides 30%-44% read access performance improvement and 2x-3.5x variation immunity at 0.7 V compared with the conventional hierarchical bit-line (HiBL) schemes. An adaptive data-aware write-assist (ADAWA) with VCS tracking is employed to further enhance the write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An adaptive voltage detector (AVD) with binary boosting control is used to mitigating gate electric over-stress. The design is implemented in UMC 40 nm low-power (40LP) CMOS technology. The 512 kb test chip operates from 1.5 V to 0.65 V, with maximum operation frequency of 800 MHz@1.1 V and 200 MHz@0.65 V. The measured power consumption is 0.5 mW/MHz (active) and 4.4 mW (standby) at 1.1 V, and 0.107 mW/MHz (active) and 0.367 mW (standby) at 0.65 V.
ESD Protection Design for Radio-Frequency Integrated Circuits in Nanoscale CMOS Technology
(2013-01-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
Nanoscale CMOS technologies have been used to implement the radio-frequency integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection on circuit performances, ESD protection at input/output pads must be carefully designed. In this work, a new proposed ESD protection design has been realized in a nanoscale CMOS process. Experimental results of the test circuits have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.
A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
(2013-01-01)
Liao, Wei-Nan
;
Lien, Nan-Chun
;
Chang, Chi-Shin
;
Chu, Li-Wei
;
Yang, Hao-I
This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive DataAware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 1.07GHz@1.2V and 887MHz@1.1V at 25 degrees C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25 degrees C.
Self-Matched ESD Cell in CMOS Technology for 60-GHz Broadband RF Applications
(2010)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
Lu, Tse-Hua
;
Hung, Ping-Fang
A self-matched ESD cell library has been implemented in a commercial sub-100nm CMOS process for 60-GHz broadband RF applications. This ESD cell library has reached the 50-Omega input/output matching to reduce the design complexity for RF circuit designer and to provide suitable electrostatic discharge (ESD) protection. Experimental results of this ESD cell library have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. This self-matched ESD cell library is easily to be used for ESD protection design in the 60-GHz broadband RF applications.
Controlled growth of the silicide nanostructures on Si bicrystal nanotemplate at a precision of a few nanometres
(2011)
Hsin, Cheng-Lun
;
Wu, Wen-Wei
;
Chu, Li-Wei
;
Hsu, Hung-Chang
;
Chen, Lih-Juann
A nanotemplate of Si bicrystal was fabricated by wafer bonding. The surface electronic energy arrangement on the surface of the Si bicrystal has been measured by scanning tunneling microscopy. The stress effect on the stepped growth of titanium silicide nanorods on Si bicrystal was observed in an ultrahigh vacuum transmission electron microscope in real time. The growth behavior of the nanorods was found to be affected by the underlying dislocation arrays significantly. For a dislocation interspacing of 3.1 nm, the dislocation arrays confined the shape of the nanoclusters and nanorods. Compared to the time of the nanorod remaining at the same length, the elongating time is more than two orders of magnitude shorter. The stepped growth behavior is attributed to the stress contour of the surface strain induced by the underlying dislocation network. This study is constructive to the basic understanding of the stress effect on the initial stage of the reaction of metals on Si and the observation may be applied to nanostructure growth for future applications and design.
Design of Analog Pixel Memory for Low Power Application in TFT-LCDs
(2011-02-01)
Chu, Li-Wei
;
Liu, Po-Tsun
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
光電工程學系
Two types of analog memory cells realized in a 3-m low temperature polycrystalline silicon (LTPS) technology are proposed to achieve low power application for thin film transistor liquid crystal displays (TFT-LCDs). By employing the inversion signal in the storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60 to 3.16 Hz with the output decay less than 0.1 V under the input data from 1 to 4 V. To further diminish threshold voltage drop from source follower structure, a compensation technique is implemented to the proposed analog memory cells. In addition, asymmetric output voltage can be also minimized by adding a reference voltage to achieve symmetric output waveform.
Transparent Amorphous Oxide Semiconductors for System on Panel Applications
(2012)
Liu, Po-Tsun
;
Chu, Li-Wei
;
Teng, Li-Feng
;
Fan, Yang-Shun
;
Fuh, Chur-Shyang
We demonstrate the applications of amorphous InGaZnO thin film transistor (a-IGZO TFT), extended from the pixel switcher/current driver, gate driver on array (GOA) to resistive random access memory (RRAM) technologies for system-on-panels (SoPs). The high-performance IGZO TFT with mobility of 13.5 cm(2)/Vs is proposed by microwave annealing process at room temperature only for 100 sec. Furthermore, an integrated gate driver scheme with the a-IGZO TFT as backbone is demonstrated in comparison with the amorphous Si TFT backplane. The rise and fall time of a-IGZO gate driver circuits is shorter than that of a-Si TFT gate driver. In addition, the ASK demodulator with a-IGZO TFT is realized successfully, and potentially to be applied for the system of low-frequency RFID tag. The study on a-IGZO RRAM reveals excellent reliability including 1000 times DC sweep endurance, 10(4) pulse endurance, 10(4) s data retention with read disturb immunity. The flexibility of a-IGZO RRAM device is also examined for flexible electronics applications.

學術出版;;Publications

Browse

Filters

Settings

Sort By

Results per page

🏛️國立陽明交通大學機構典藏

Search Results