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Author: search.filters.author.Dai, Chia-TsenSubject: search.filters.subject.silicon-controlled rectifier (SCR)

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Now showing 1 - 4 of 4
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    Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25-mu m 60-V/5-V BCD Technology
    (2017-08-01)
    Dai, Chia-Tsen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this brief. Owing to multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic silicon-controlled rectifier path featuring a very low holding voltage is found in the experimental silicon chip. Such a parasitic path is first reported in the literature. It may influence the electrostatic discharge robustness of CMOS IC products with the HV and LV circuits integrated together. Thus, the layout rules at the HV and LV interface should be carefully defined to avoid the occurrence of an unexpected parasitic path.
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    Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications
    (2018-02-01)
    Dai, Chia-Tsen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The modified silicon-controlled rectifier (SCR) fabricated in a 0.25-mu m high-voltage (HV) bipolar-CMOS-DMOS (BCD) technology has been proposed to seek for both effective electrostatic discharge (ESD) protection and latchup immunity. Experimental results show that one of the proposed SCRs has a high holding voltage of up to similar to 30 V in the 100-ns transmission line pulsing measurement results. However, through the experimental verification by using the transient latchup test, the holding voltage of such proposed device decreases to similar to 20 V. It is due to the increased bipolar junction transistor current gains of the SCR path induced by the Joule-heating effect in the long-term measurement. For 20-V circuit applications, the ESD robustness of the proposed SCR with a holding voltage of similar to 20 V is lower than that of stacked low-voltage p-type MOS in the previous studies. Developing special modification of such HV devices is inefficient to achieve both effective ESD protection and latchup-free design in this 0.25-mu m HV BCD technology.
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    ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC
    (2016-05)
    Dai, Chia-Tsen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    For high-voltage (HV) applications, the electrostatic discharge (ESD) protection design using a traditional HV device, such as laterally diffused MOSFETs, usually consumes large silicon area to meet sufficient ESD specification. In this paper, an area-efficient ESD protection design with stacked highholding- voltage silicon-controlled rectifier (HHVSCR) is proposed and verified in a 0.25-mu m 5/60 V Bipolar-CMOS-DMOS process. The proposed HHVSCR is fabricated in low-voltage wells and has the characteristics of HHV and high failure current with the same silicon area as the traditional SCR. From the experimental results, the proposed HHVSCR stacking structure can fit the desired ESD protection design window for the 60 V pins of a battery-monitoring IC and successfully protect these 60 V pins against 7-kV human-body-mode ESD stress.
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    Self-Protected LDMOS Output Device with Embedded SCR to Improve ESD Robustness in 0.25-mu m 60-V BCD Process
    (2013)
    Huang, Yu-Ching
    ;
    Dai, Chia-Tsen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    For high-voltage output driver, the lateral DMOS (LDMOS) is often used for both output function operation and self-protection against electrostatic discharge (ESD) events. In this work, a new structure of LDMOS output device with embedded SCR has been proposed and verified in a 0.25-mu m 60-V BCD process. This new structure, with additional p(+) and n(+) implantation regions added between the drain contact and poly-gate of LDMOS, can keep it stably in the high-current holding region after snapback. By using this structure, the LDMOS can provide high enough self-protected ESD robustness for applications in the high-voltage output drivers.