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Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
(2011-09-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
This paper analyzes stability and variability of ultrathin-body (UTB) SOI subthreshold SRAMs considering line- edge roughness (LER), work function variation (WFV), and temperature sensitivity. The intrinsic advantages of UTB SOI technology versus bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are analyzed. Compared with LER, WFV causes comparable threshold voltage variation and much smaller subthreshold swing fluctuation, hence less impact on the UTB SOI subthreshold SRAMs. Even considering LER, the Lg = 40 nm UTB SOI 6T subthreshold SRAM cells still provide sufficient margin (mu RSNM/sigma RSNM > 6 at Vdd = 0.3 similar to 0.4 V) while the bulk subthreshold SRAMs with RDF fail to maintain adequate margin. Increasing temperature will increase the Vread,0 and decrease RSNM because of the degraded subthreshold swing. The RSNM of UTB SOI subthreshold SRAMs showless temperature sensitivity compared with that of bulk subthreshold SRAMs. Due to larger body effect, the back-gating technique is more efficient for the Lg = 40 nm and 25 nm UTB SOI subthreshold SRAMs compared with the bulk counterparts. By using lower threshold voltage devices with dual band-gapwork functions, the Lg = 25 nm UTB SOI subthreshold SRAMs show 31.9% reduction in sigma RSNM and 55% improvement in mu RSNM/sigma RSNM.
Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits
(2012-08-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing (S.S.) and comparable trap-induced V-T shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way NAND, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause similar to 24%-27% and similar to 13%-15% variations in leakage and delay at V-dd = 0.4 V, respectively, for the logic circuits evaluated.
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications
(2012-12-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper investigates the impact of intrinsic random variability on the robustness of sense amplifier (SA) for fin-shaped field-effect transistor (FinFET) subthreshold static random access memory (SRAM) applications. We employ a model-assisted statistical approach to consider both fin line edge roughness (fin LER) and work function variation, which are regarded as the major variation sources in an advanced FinFET device. Our results indicate that fin LER dominates the overall variability of subthreshold SA robustness and sensing margin. In addition, it is observed that the offset voltage (V-OS) of current latch SA calculated solely from threshold voltage (V-T) mismatch underestimates the actual variation and is shown to be optimistic. For large-signal single-ended inverter sensing, we find that sense "0" hinders the allowable sensing margin and needs to be carefully designed. Compared with bulk CMOS, the superior electrostatic integrity and variability of FinFET enhance the feasibility of differential sensing in subthreshold SRAM applications.
Ultra-Low Voltage Mixed TFET-MOSFET 8T SRAM Cell
(2014-01-01)
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
In this work, we propose a mixed TFET-MOSFET 8T SRAM cell comprising MOSFET cross-coupled inverters, dedicated TFET read stack and TFET write access transistors. Exploiting both the merits of TFET and MOSFET devices, the proposed SRAM cell provides significant improvement in SRAM stability, V-min and performance. The proposed cell is evaluated and compared with the conventional MOSFET 8T cell and pure TFET 8T cell using mixed mode TCAD simulations. The results indicate that the proposed mixed TFET-MOSFET cell topology is viable for ultra-low voltage operation.
Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FET
(2015-05)
Hsu, Chih-Wei
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
;
電子工程學系及電子研究所
This paper investigates and compares the impacts of metal-gate work-function variation (WFV) on III-V heterojunction tunnel FET (HTFET), homojunction TFET, and FinFET devices using a novel Voronoi method to capture the realistic metal-gate grain patterns for Technology Computer Aided Design atomistic simulations. Due to the broken-gap nature, HTFET shows significantly steeper subthreshold slope and higher susceptibility to WFV near OFF state. For ON current variation, both the HTFET and homojunction TFET show better immunity to WFV than the III-V FinFET. Device design using source-side underlap to mitigate the impact of WFV on HTFET is also assessed.
Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
(2015)
Wu, Tse-Ching
;
Chen, Chien-Ju
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we investigate the hybrid TFET-FinFET latch circuits and compare the clock-to-Q delay, dynamic energy, leakage power and energy-delay product (EDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. Four types of latch circuits are evaluated, including standard clocked CMOS latch (SCCL), low-voltage (CMOS)-M-2 latch (LVCL), master-slave transmission-gate latch pair (MTLP) and pulse-triggered latch (PTL). In the hybrid design, TFETs are used for critical path to reduce the clock-to-Q delay, and FinFETs are used for the rest of the circuits to reduce the power consumption. The hybrid latch circuits are shown to offer comparable or better clock-to-Q delays while exhibiting superior EDP compared with all TFET implementations. Among the four types of latch circuits, the hybrid TFET-FinFET LVCL exhibits the most significant clock-to-Q delay and EDP improvements at low operating voltage (< 0.30V). With work function variation (WFV) and fin line-edge roughness (LER), the hybrid LVCL exhibits superior and comparable EDP variability compared with all FinFET and all TFET implementations at 0.25V.
Investigation of BTI Reliability for Monolithic 3D 6T SRAM with Ultra-thin-body GeOI MOSFETs
(2016)
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates the impacts of negative and positive bias temperature instabilities (NBTI and PBTI) on the stability and performance of ultra-thin-body (UTB) GeOI 6T SRAM cells integrated in monolithic 3D scheme with interlayer coupling. Various bitcell layouts with different gate alignments of transistors from distinct layers are investigated. The worst case stress scenarios for read and write operations are analyzed. The optimized monolithic 3D UTB GeOI SRAM with the pull-down NFET tier stacked over the pull-up PFET tier and under forward PFET back-gate bias shows improvements in read stability and cell read-access time compared with the 2D UTB GeOI SRAM. Monolithic 3D UTB GeOI SRAM with high threshold voltage (Vth) design can enhance the improvements in stability and performance over 2D SRAM. Moreover, the optimized monolithic 3D UTB GeOI SRAM can mitigate the temporal degradations in stability and performance due to BTI stress because the BTI induced Vth degradations can be suppressed by interlayer coupling in monolithic 3D scheme.
Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and Logic Circuits
(2014)
Chen, Chien-Ju
;
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and logic circuits operating in near-threshold region. The impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, two-way NAND delay, switching energy and leakage power are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations. The results indicate that WFV and fin LER have different impacts on ION and IOFF. The delay variability of two-way NAND is aggravated by the Miller capacitance of TFET and FinFET devices.
UTB GeOI 6T SRAM Cell and Sense Amplifier considering BTI Reliability
(2015)
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates the impacts of negative and positive bias temperature instabilities (NBTI and PBTI) on the stability of ultra-thin-body (UTB) GeOI 6T SRAM cell and performance of sense amplifier compared with the SOI counterparts. Worst case stress scenarios for read and write operations are analyzed. For UTB GeOI SRAMs, PBTI dominates the degradations in read static noise margin (RSNM), while for UTB SOI SRAMs, NBTI dominates the degradations in RSNM. Write static noise margin (WSNM) only slightly degrades due to NBTI and PBTI. Current latch sense amplifier (CLSA) and voltage latch sense amplifier (VLSA) are analyzed considering NBTI/PBTI for GeOI and SOI devices. GeOI CLSA and VLSA show smaller word-line to SAE buffer delay (T-BL) and sense amplifier sensing delay (T-SA) than the SOI counterparts. As aging time increases, GeOI CLSA and VLSA show larger degradations of T-SA than the SOI counterparts.
Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap
(2016)
Hu, Vita Pi-Ho
;
Lo, Chang-Ting
;
Sachid, Angada B.
;
Su, Pin
;
Hu, Chenming
Corner spacer design is investigated to improve the performance of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap compared with the all vacuum and all nitride spacer devices. All vacuum spacer devices with low permittivity reduce fringing capacitance and improve performance. However, for gate-to-source/drain underlap InGaAs-OI FinFET, all vacuum spacer device degrades source/drain resistance (Rsd) and ON current (Ion), thus exhibiting slight improvement in inverter delay compared with the all nitride spacer device. Corner spacer design comprising of high-k and low-k composite spacer is proposed to optimize Rsd and capacitance, and hence improve delay. Various lengths and heights of corner spacer for InGaAs-OI FinFET with different underlap length and fin height aspect ratio are investigated to optimized performance. The optimized corner spacer design is: (a) the length of corner spacer (Lcorner) is approximately equal to underlap length (Lun), and (b) the height of corner spacer (Hcorner) is proportional to the sum of fin height (Hfin) and gate oxide thickness (Tox). Compared with the all vacuum spacer InGaAs-OI FinFET with Lun = 6 nm, the optimized corner spacer design exhibits 36% and 10% improvements in Ion and inverter delay, respectively.

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