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Impacts of Nanocrystal Location on the Operation of Trap-Layer-Engineered Poly-Si Nanowired Gate-All-Around SONOS Memory Devices
(2011-07-01)
Luo, Cheng-Wei
;
Lin, Horng-Chih
;
Lee, Ko-Hui
;
Chen, Wei-Chen
;
Hsu, Hsing-Hui
Trap-layer-engineered poly-Si nanowire silicon-oxide-nitride-oxide-silicon (SONOS) devices with a gate-all-around (GAA) configuration were fabricated and characterized. For the first time, a clever method has been developed to flexibly incorporate Si-nanocrystal (NC) dots in different locations in the nitride layer. Three types of poly-Si GAA SONOS devices with Si-NC dots embedded in the block oxide/nitride interface, the middle of the nitride, and the nitride/tunnel oxide interface, respectively, by in situ deposition were fabricated and investigated in this paper. Our results indicate that the optimal NC location appears to be somewhere between the middle and bottom interfaces of the nitride layer.
A Novel Charge-Trapping-Type Memory With Gate-All-Around Poly-Si Nanowire and HfAlO Trapping Layer
(2013-03-01)
Lee, Ko-Hui
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Hf-based charge-trapping (CT) layers, including HfO2 and HfAlO, were employed in the fabrication of a CT-type memory with gate-all-around (GAA) poly-Si nanowire channels. It is shown that the GAA configuration can greatly enhance the programming/erasing efficiency as compared with the conventional planar scheme. It is also shown that the incorporation of Al into the dielectric can further improve the retention and endurance characteristics over the counterparts with a HfO2 trapping layer. Retardation of the recrystallization of the dielectric film with Al incorporation is postulated to be responsible for these observations.
Performance Enhancement of Thin-Film Transistors With Suspended Poly-Si Nanowire Channels by Embedding Silicon Nanocrystals in Gate Nitride
(2012-03-01)
Kuo, Chia-Hao
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, we fabricated and characterized thin-film transistors with a suspended poly-Si nanowire (NW) channel and gate nitride with embedded silicon nanocrystals (Si NCs). The embedded Si NCs increase the surface roughness, thus reducing the adhesive force as the nitride is in contact with the poly-Si NW channel during the operation. Such a feature results in a reduction in pull-in voltage and sharper pull-out behavior. Moreover, this approach also greatly improves the endurance characteristics of the devices.
Read Characteristics of Independent Double-Gate Poly-Si Nanowire SONOS Devices
(2011-11-01)
Lin, Horng-Chih
;
Lin, Zer-Ming
;
Chen, Wei-Chen
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
This paper investigates the read operation of poly-Si nanowire silicon-oxide-nitride-oxide-silicon devices with independent double-gate (IDG) configuration. The device features oxide-nitride-oxide (ONO) stack as the charge storage medium in one of the two gated sides with pure oxide in the other. Owing to the IDG feature, the shift in the device's transfer characteristics due to a change in the amount of storage charges can be sensed with two different modes, which have one of the two gates applied with a sweeping bias (driving gate) and the other with a fixed bias (control gate). Our analysis and experimental data show that a larger memory window is obtained when the gate of the ONO side is used as the driving gate. Moreover, the memory window of this mode is essentially independent of the bias applied to the control gate. Based on this finding, a novel Flash structure featuring IDG cells with a common control gate is proposed.
Impacts of Multiple-Gated Configuration on the Characteristics of Poly-Si Nanowire SONOS Devices
(2011-03-01)
Hsu, Hsing-Hui
;
Lin, Horng-Chih
;
Luo, Cheng-Wei
;
Su, Chun-Jung
;
Huang, Tiao-Yuan
In this paper, we have proposed a simple and novel way to fabricate poly-Si nanowire (NW)-silicon-oxide-nitride-oxide-silicon (SONOS) devices with various gate configurations. Three types of devices having various gate configurations, such as side gated, O-shaped gated OG, and gate-all-around (GAA), were successfully fabricated and characterized. The experimental results show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices, as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest programming/erasing efficiency, largestmemory window, and best endurance/retention characteristics, highlighting the potential of such scheme for future SONOS applications.
A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse-T gate
(2008-07-01)
Lin, Horng-Chih
;
Hsu, Hsing-Hui
;
Su, Chun-Jung
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
A novel multiple-gate field-effect transistor with poly-Si nanowire (NW) channels is proposed and fabricated using a simple process flow. In the proposed structure, poly-Si NW channels are formed with sidewall spacer etching technique, and are surrounded by an inverse-T-gate and a top gate. When the two gates are connected together to drive the NW channels, dramatic performance enhancement as compared with the cases of single-gate operation is observed. Moreover, subthreshold swing as low as 103 mV/dec at Vd = 2 V is recorded. Function of using the top gate bias to modulate the threshold voltage of device operation driven by the inverse-T gate biases is also investigated in this letter.
Fabrication and Characterization of Multiple-Gated Poly-Si Nanowire Thin-Film Transistors and Impacts of Multiple-Gate Structures on Device Fluctuations
(2008-11-01)
Hsu, Hsing-Hui
;
Liu, Ta-Wei
;
Chan, Leng
;
Lin, Chuan-Ding
;
Huang, Tiao-Yuan
Several types of poly-Si nanowire (NW) thin-film transistors (TFTs) with multiple-gated (MG) configuration were demonstrated and characterized. These devices were fabricated with simple methods without resorting to costly lithographic tools and processes. The fabricated trigated devices show a low subthreshold swing (SS) of around 100 mV/dec and on/off current ratio higher than 10(8). These results clearly indicate the effectiveness of MG scheme in enhancing the device performance. Furthermore, a multiple-channel scheme was demonstrated to further increase the drive current without compromising device performance. Finally, the impact of MG on the variation of NWTFT characteristics is investigated with a clever method that allows the fabrication of test structures with identical NW channel but different gate configurations. The results,clearly show that the variation could be reduced by increasing the portion of NW channel surface that is modulated by the gate.
Threshold-Voltage Fluctuation of Double-Gated Poly-Si Nanowire Field-Effect Transistor
(2009-03-01)
Hsu, Hsing-Hui
;
Lin, Horng-Chih
;
Chan, Leng
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
In this letter, the fluctuation characteristics of polycrystalline silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) with independently controlled double-gate configuration were studied. The defects existing in the NW channels are identified as one of the major sources for the fluctuation. The passivation of these defects by plasma treatment is shown to be effective for reducing the fluctuation. We have also found that the fluctuation is closely related to the operation modes. When only one of the gates is employed as the driving gate to control the switching behavior of the device, an optimum bias for the other gate can be found for minimizing the fluctuation.
Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness
(2009-06-01)
Lin, Horng-Chih
;
Chen, Wei-Chen
;
Lin, Chuan-Ding
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels and two independent gates. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. Our results indicate that dramatic performance enhancement is feasible when the thickness of the NW channel is sufficiently thin, and the two conduction channels in the NW structure are operating simultaneously.
Origins of Performance Enhancement in Independent Double-Gated Poly-Si Nanowire Devices
(2010-04-01)
Hsu, Hsing-Hui
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we characterize and compare the characteristics of a poly-Si nanowire (NW) device with independent double-gated configuration under different operation modes. In the device, the tiny NW channels are surrounded by an inverted-T-shaped gate and a top gate. It is found that the device under double-gate (DG)mode exhibits significantly better performance with respect to the two single-gate (SG) modes, as indicated by a higher current drive than the combined sum of the two SG modes and a smaller subthreshold swing of less than 100 mV/dec. Origins of such improvement have been identified to be due to the elimination of the back-gate effect as well as an enhancement in the effective mobility with the DG operation.

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