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Fabrication and Characterization of Film Profile Engineered ZnO TFTs With Discrete Gates
(2015-05-01)
Lyu, Rong-Jhe
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
By virtue of the film-profile engineering scheme and properly designed device structure, ZnO TFTs with discrete bottom gates and sub-micron channels were fabricated and characterized. In the fabrication, a suspended bridge constructed over the bottom gate is used to tailor the profile of subsequently deposited films. Superior electrical characteristics in terms of ultrahigh ON/OFF current ratio (similar to 10(10)), steep sub-threshold swing (66 similar to 108 mV/dec), and very low off-state leakage current are demonstrated with the fabricated devices. Effects of channel lengths on the device characteristics are also explored. Because of more effective shadowing of the depositing species with a longer suspended bridge, the deposited films become thinner at the central channel. As a result, the device shows more positive turn-on voltage and better subthreshold swing with increasing channel length.
A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO2/poly-gate complementary metal oxide semiconductor technology
(2010-04-01)
Weng, Wu-Te
;
Lee, Yao-Jen
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
This study examines the effects of plasma-induced damage (PID) both on advanced SiO2/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. (C) 2010 Elsevier Ltd. All rights reserved.
A study on low temperature transport properties of independent double-gated poly-Si nanowire transistors
(2010-10-29)
Chen, Wei-Chen
;
Lin, Horng-Chih
;
Lin, Zer-Ming
;
Hsu, Chin-Tsai
;
Huang, Tiao-Yuan
Employing mix-and-match lithography of I-line stepper and e-beam direct writing, independent double-gated poly-Si nanowire thin film transistors with channel lengths ranging from 70 nm to 5 mu m were fabricated and characterized. Electrical measurements performed under cryogenic ambient displayed intriguing characteristics in terms of length dependent abrupt switching behavior for one of the single-gated modes. Through simulation and experimental verification, the root cause for this phenomenon was identified to be the non-uniformly distributed dopants introduced by ion implantation.
Impact of gate dielectrics and oxygen annealing on tin-oxide thin-film transistors
(2016-04-01)
Zhong, Chia-Wen
;
Lin, Horng-Chih
;
Tsai, Jung-Ruey
;
Liu, Kou-Chen
;
Huang, Tiao-Yuan
In this work, we study the impact of gate dielectrics on the characteristics of bottom-gated tin-oxide thin-film transistors annealed in an oxygen ambience at 300 degrees C for various periods. SiO2, HfO2, and Al2O3 are employed as the gate dielectric in the test devices. The results show that the devices will start exhibiting p-type conduction behavior as the annealing reaches a specific time period which is closely related to the underlying gate dielectric, and the device characteristics can be improved as the annealing proceeds further. Nonetheless, a prolonged annealing may cause degradation of the devices. High hole mobility (3.33 cm(2)V(-1)s(-1)), low threshold voltage (1.95 V), and excellent I-on/I-off ratio (similar to 10(4)) are achieved on SnO TFTs with a SiO2 gate dielectric after an annealing of 30 min. (C) 2016 The Japan Society of Applied Physics
100-nm IGZO Thin-Film Transistors With Film Profile Engineering
(2014-06-01)
Lin, Horng-Chih
;
Shie, Bo-Shiuan
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
100-nm indium-gallium-zinc-oxide (IGZO) thin-film transistors were fabricated with a one-mask process, which takes the advantage of photoresist trimming technique and the concept of film profile engineering (FPE). With I-line-based photolithography, a device with channel length of 97 nm has been successfully fabricated. The FPE device contains a conformal Al2O3 gate oxide, concave IGZO channel, and discrete source/drain (S/D) Al contacts. Good device characteristics including a high-ON/OFF current ratio (>10(7)) and good subthreshold swing (140 mV/decade) are obtained. Nonetheless, high-S/D series resistance presents a key issue that needs to be addressed for further device performance improvement.
High-Performance Submicrometer ZnON Thin-Film Transistors With Record Field-Effect Mobility
(2016-03)
Kuan, Chin-I
;
Lin, Horng-Chih
;
Li, Pei-Wen
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
In this letter, we demonstrate 0.6-mu m ZnON thin-film transistors (TFTs) with the field-effect mobility of 71 cm(2)/V-sec, which to the best of our knowledge is the highest value ever reported on submicrometer oxide-semiconductor TFTs. The drive current, field-effect mobility, and subthreshold slope of ZnON TFTs are significantly improved as compared with their counterpart ZnO TFTs of the same channel dimensions and structure. Such an improvement in the field-effect mobility primarily results from a considerable reduction in the series source/drain (S/D) resistances because of suppression in an interfacial layer formation between Al S/D pads and the channel layer.
Downscaling Metal-Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach
(2017-03)
Lyu, Rong-Jhe
;
Shie, Bo-Shiuan
;
Lin, Horng-Chih
;
Li, Pei-Wen
;
Huang, Tiao-Yuan
We report an exquisite, film- profileengineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of 7.9x10(7) and 4.2x10(7), superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometerscale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics.
Impact of thermal oxygen annealing on the properties of tin oxide films and characteristics of p-type thin-film transistors
(2016-01)
Zhong, Chia-Wen
;
Lin, Horng-Chih
;
Liu, Kou-Chen
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
In this work, we study the properties of tin oxide films, which were annealed in oxygen ambient for various periods. The as-deposited tin oxides are tin-dominant and, from the Hall measurements, they are of the n-type with high electron concentrations (>10(19) cm(-3)) and would change to the p-type when the oxygen annealing is sufficiently long. We have also found that changes in the structure and crystallinity of the channel layer can be clearly observed by X-ray diffraction analysis and optical microscopy. On the basis of the observations, a physical scheme is proposed to describe the evolution of the electrical performance of oxygen-annealed devices. A hole mobility of 3.24 cm(2) V-1 s(-1), a subthreshold swing of 0.43V/dec, a threshold voltage of 1.4V, and an on/off current ratio larger than 10(3) are obtained as the channel is transformed into SnO. (C) 2016 The Japan Society of Applied Physics
A Film-Profile-Engineered 3-D InGaZnO Inverter Technology With Systematically Tunable Threshold Voltage
(2016-09)
Lyu, Rong-Jhe
;
Lin, Horng-Chih
;
Li, Pei-Wen
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
In this paper, a new depletion-load metal oxide-based inverter with 3-D structure is realized with film-profile-engineered InGaZnO (IGZO) thin-film transistors (TFTs). The proposed inverter possesses vertically stacked load and drive TFTs whose threshold voltage can be flexibly adjusted into a wide range of -2.3-1 V through merely adjusting the geometric parameters without the necessity of additional processes or masks. The 3-D IGZO inverters constructed through the proposed technology demonstrate full-swing switching with voltage gains up to 19 V/V under an operation voltage of 9 V. The 3-D inverters can not only reduce the footprint but also promote the resistance toward light-induced instability.
Novel BEOL InGaZnO R-load-Type Logic-Gate Technology
(2014)
Chan, Chin-Wen
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電機學院
;
電子工程學系及電子研究所
N-channel InGaZnO (IGZO) inverters with a resistor-load were fabricated with film-profile engineering (FPE). In this scheme the profiles of the deposition films contained in the device are tailored to adjust its operation characteristics. The fabricated drive thin-film transistors (TFTs) show steep subthreshold swing (88 mV/dec) and high on/off current ratio (> 10(8)). Functional operation of the inverters is demonstrated with this simple scheme.

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