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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Ker, MDHas files: No

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    Active device under bond pad to save I/O layout for high-pin-count SOC
    (2003-01-01)
    Ker, MD
    ;
    Peng, JJ
    ;
    Jiang, HC
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-mum one-poly-four-metal (1P4M) 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the effect of bonding stress on the active devices under the pads. Threshold voltage, off-state drain current, and gate leakage current of these devices under bond pads have been measured. After assembled in wire bond package, the measurement results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied on saving layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count system-on-a-chip (SOC).
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    Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
    (1996-09-01)
    Ker, MD
    ;
    Wu, CY
    ;
    Cheng, T
    ;
    Chang, HH
    ;
    電子工程學系及電子研究所
    Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed, The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit, Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.
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    Novel input ESD protection circuit with substrate-triggering technique in a 0.25-mu m shallow-trench-isolation CMOS technology
    (1998)
    Ker, MD
    ;
    Chen, TY
    ;
    Wu, CY
    ;
    Tang, H
    ;
    Su, KC
    A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD-protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 Angstrom) of the input stage in a 0.25-mu m CMOS technology and sustain an ESD level above 2000V without extra process modification.
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    Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits
    (2000)
    Ker, MD
    ;
    Jiang, HC
    ;
    Chang, CY
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance.
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    New diode string design with very low leakage current for using in power supply ESD clamp circuits
    (2000)
    Ker, MD
    ;
    Lo, WY
    ;
    Chang, HH
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A new diode string design with very low leakage current is proposed for using in the on-chip power supply ESD electrostatic discharge) clamp circuits. Three traditional designs of the stacked diode strings used in the power supply ESD clamp circuits are also fabricated in the same test chip to verify the improvement of this new design. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the leakage current of this new proposed diode string with 6 stacked diodes under a 5-V (3.3-V) forward bias condition can be controlled below 2.1 (1.07) nA at an environment temperature of 125 degrees C. The blocking voltage of this new diode string design with NCLSCR can be linearly adjusted by simply changing the number of the stacked diodes in the diode string for application across the power lines with different voltage levels to achieve the whole-chip ESD protection scheme.
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    Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications
    (2000)
    Ker, MD
    ;
    Chen, TY
    ;
    Wu, CY
    ;
    Chang, HH
    ;
    電子工程學系及電子研究所
    An on-chip ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-precision applications. A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices has been developed to keep the total input capacitance almost constant (within 1% variation), even if the analog signal has an input dynamic range of 1V. The device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mu m/mu m) in a 0.35-mu m silicided CMOS process, but it can sustain the HEM (MM) ESD level of up to 6kV (400V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to 1.0 pF (including the bond pad capacitance) for high-frequency applications.
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    ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design
    (2001)
    Chen, TY
    ;
    Ker, MD
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The operation principles of gate-driven design and substrate-triggered design for ESD (ElectroStatic Discharge) protection are first explained by energy-band diagrams in this paper. The on-chip ESD protection devices realized in 0.18-mum and 0.35-mum CMOS processes are used to verify the efficiency of gate-driven or substrate-triggered designs. The substrate-triggered design can effectively and continually improve ESD robustness of protection devices than the gate-driven design. The HEM (Human-Body-Model) ESD level of NMOS with a W/L of 300 mum/0.3 mum can be improved from the original 0.8kV to become 3.3kV by the substrate-triggered design. But, the gate-driven design cannot continually improve the ESD level of the same device in the subquarter-micron CMOS process.
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    Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technology
    (2001)
    Ker, MD
    ;
    Hong, KK
    ;
    Chen, TY
    ;
    Tang, H
    ;
    Huang, SC
    Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-mum partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.
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    Level shifters for high-speed 1-v to 3.3-v interfaces in a 0.13-mu m Cu-Interconnection/Low-k CMOS technology
    (2001)
    Wang, WT
    ;
    Ker, MD
    ;
    Chiang, MC
    ;
    Chen, CH
    ;
    電子工程學系及電子研究所
    Level shifters for 1.0-V to 3.3-V high-speed interfaces are proposed. Level-up shifter uses zero-Vt 3.3-V NMOSs as voltage clamps to protect 1.0-V NMOS switches from high voltage stress across the gate oxide. Level-down shifter uses 3.3-V NMOSs as both pull-up and pull-down devices with supply voltage of 1.0-V and gate voltage swing from 0-V to 3.3-V. The zero-Vt NMOS is a standard MOSFET device in a 0.13-mum CMOS process without adding extra mask or process step to realize it. Level-up transition from 0.9-V to 3.6-V takes only 1 ns in time, and the level-down transition has no minimum core voltage limitation. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.