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Active device under bond pad to save I/O layout for high-pin-count SOC
(2003-01-01)
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-mum one-poly-four-metal (1P4M) 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the effect of bonding stress on the active devices under the pads. Threshold voltage, off-state drain current, and gate leakage current of these devices under bond pads have been measured. After assembled in wire bond package, the measurement results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied on saving layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count system-on-a-chip (SOC).
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
(1996-09-01)
Ker, MD
;
Wu, CY
;
Cheng, T
;
Chang, HH
;
電子工程學系及電子研究所
Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed, The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit, Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.
Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area
(1998-06-01)
Ker, MD
;
Wu, CY
;
Huang, CC
;
Chen, TY
;
電子工程學系及電子研究所
A new multiple-cell square-type layout design is proposed to realize the large-dimension output transistors for submicron low-voltage CMOS ICs. By using this layout design, the layout area of CMOS output buffers can be effectively reduced 30-40% with respect to the traditional finger-type layout. The drain-to-bulk parasitic capacitance of the output transistors is also reduced 40% by this square-type layout. Experimental results in a 0.6 mu m CMOS process have shown that the maximum driving (sinking) capability per unit layout area of a CMOS output buffer realized by the proposed multiple-cell square-type layout is improved 54% (34%) more than that by the traditional finger-type layout. The human-body-model (machine-model) ESD robustness per unit layout area of the CMOS output buffer realized by the proposed multiple-cell square-type layout is increased 25.2% (17.3%) as comparing to that by the traditional finger-type layout. (C) 1998 Published by Elsevier Science Ltd. All rights reserved.
Improved output ESD protection by dynamic gate floating design
(1998-09-01)
Chang, HH
;
Ker, MD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A dynamic gate Boating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-mu m CMOS process.
Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology
(1999-02-01)
Chang, HH
;
Ker, MD
;
Wu, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel dynamic-floating-gate technique is proposed to improve ESD robustness of the CMOS output buffers with small driving/sinking currents. This dynamic-floating-gate design can effectively solve the ESD protection issue which is due to the different circuit connections on the output devices. By adding suitable time delay to dynamically float the gates of the output NMOS/PMOS devices which are originally unused in the output buffer, the human-body-model (machine-model) ESD failure threshold of a 2-mA output buffer can be practically improved from the original 1.0 kV (100 V) up to greater than 8 kV (1500 V) in a 0.35-mu m bulk CMOS process. (C) 1998 Elsevier Science Ltd. All rights reserved.
New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness
(1999-03-01)
Ker, MD
;
Chen, TY
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New layout design to effectively reduce the layout area of CMOS output transistors but with higher driving capability and better ESD reliability is proposed. The output transistors of large device dimensions are assembled by a plurality of the basic layout cells, which have the square, hexagonal or octagonal shapes. The output transistors realized by these new layout styles have more symmetrical device structures, which can be more uniformly triggered during the ESD-stress events. With theoretical calculation and experimental verification, both higher output driving/sinking current and stronger ESD robustness of CMOS output buffers can be practically achieved by the proposed new layout styles within a smaller layout area in the non-silicided bulk CMOS process. The output transistors assembled by a plurality of the proposed layout cells also have a lower gate resistance and a smaller drain capacitance than that realized by the traditional finger-type layout. (C) 1999 Elsevier Science Ltd. All rights reserved.
Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
(2000-03-01)
Ker, MD
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered by noise pulses when the ICs are operated in the application systems. A cascoded design is therefore proposed to safely apply the LVTSCR devices for whole-chip ESD protection in CMOS ICs without causing unexpected operation errors or latchup danger. The temperature dependence on the holding voltage of the cascoded LVTSCRs has been investigated in detail. From the experimental verification, the cascoded LVTSCRs can be fully turned on within a time below 20 ns. The ESD robustness per layout area of the three-cascoded LVTSCRs can be 0.83 V/mu m(2) in a 0.35-mu m silicide CMOS process without using the extra silicide-blocking and ESD-implant masks, whereas the ESD robustness of the gate-grounded NMOS is only 0.25 V/mu m(2). Such cascoded LVTSCRs with a tunable holding voltage greater than VDD can provide CMOS ICs with effective component-level ESD protection but without causing catchup danger if it is accidentally triggered by the system-level overshooting or undershooting noise pulses. (C) 2000 Elsevier Science Ltd. All rights reserved.
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
(2000-04-01)
Ker, MD
;
Lo, WY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new design on the diode string with very tow leakage current is proposed for using in the ESD clamp circuits across the power rails. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the Leakage current of this new diode string with six stacked diodes at 5-V (3.3-V) forward bias can be reduced to only 2.1 (1.07) nA at a temperature of 125 degrees C in a 0.35-mu m silicide CMOS process, whereas the previous designs have a leakage current in the order of mA, The total blocking voltage of this new design with NCLSCR can be linearly adjusted by changing the number of the stacked diodes in the diode string without causing latch-up danger across the power rails. From the experimental results, the human-body-model ESD level of the ESD clamp circuit with the proposed low-leakage diode string is greater than 8 kV in a 0.35-mu m silicide CMOS process by using neither the ESD-implantation nor the silicide-blocking process modifications.
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
(2000-08-01)
Ker, MD
;
Chen, TY
;
Wu, CY
;
Chang, HH
;
電子工程學系及電子研究所
An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mu m/mu m) in a 0.35-mu m silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to 1.0 pF (including the bond-pad capacitance) for high-frequency applications.
Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard
(2001-03-01)
Ker, MD
;
Sung, YY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A hardware.firmware co-design solution in an S-bits microcontroller has been proposed to practically fix the system-level electrostatic discharge (ESD) issue on the keyboard products. By including the especial ESD sensors and an additional ESD flag into the chip, the fast electrical transient due to the system-level ESD zapping on the keyboard can be detected. The firmware stored in the ROM of the 8-bits microcontroller is designed to automatically check the ESD flag to monitor the abnormal conditions in system operations. If the keyboard is upset or locked up by a system-level ESD transient, the microcontroller can be quickly recovered to a known and stable state. The 8-bits microcontroller with such a hardware/firmware co-design solution has been fabricated in a 0.45-mum CMOS process. The system-level ESD susceptibility of the keyboard with this 8-bits microcontroller has been improved from the original +/-2 kV (+/-4 kV) to become greater than +/-8 kV (+/- 15 kV) in the contact-discharge (air-discharge) ESD zapping. (C) 2001 Elsevier Science Ltd. All rights reserved.

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