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Correlation of stress-induced leakage current with generated positive trapped charges for ultrathin gate oxide
(1998-02-01)
Lin, YH
;
Lee, CL
;
Lei, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, the evidence of the stress-induced leakage current related with the stress-generated positive trapped charges is presented and investigated. It is shown that the centroid of the positive trapped charges, which depends on the polarity of the stress current, affects the magnitude of the leakage current. And the trapping density of positive charges, which is determined by the final stress applied on the oxide, determines the final level of the leakage currents.
Characterization of polysilicon oxides thermally grown and deposited on the polished polysilicon films
(1998-04-01)
Lei, TF
;
Cheng, JY
;
Shiau, SY
;
Chao, TS
;
Lai, CS
This work examines the characteristics of polyoxides thermally grown and deposited an polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology Tot polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping, rate, lower density of trapped charges, and markedly higher charge to breakdown (Q(bd)) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides' upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide.
Comparison of N-2 and NH3 plasma passivation effects on polycrystalline silicon thin-film transistors
(1998-07-01)
Lee, YS
;
Lin, HY
;
Lei, TF
;
Huang, TY
;
Chang, TC
The passivation effects of pure N-2 plasma on polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been studied and compared with those of NH3 plasma. We found that, similar to the recently-proposed NH3 plasma passivation, N-2 plasma passivation can also effectively improve device parameters such as field effect mobility, threshold voltage subthreshold swing, off current, and on/off current ratio. While the improvement of NH3-passivated devices can be attributed to both hydrogen and nitrogen passivation effects, nitrogen passivation alone is mainly responsible for the improvement of N-2-passivated devices. Zn addition, we round that N-2-passivated devices exhibit much better hot-carrier reliability than NH3-passivated devices. The better hot-carrier reliability of N-2-passivated devices can be explained by the formation of strong Si-N bonds which are difficult to break, while effectively eliminating the weaker N-H bonds, which are inevitable in NH3-passivated devices. The results of a Fourier. transform infrared (FTIR) spectrum analysis performed in this study are consistent with this proposition.
Controlling the diffusion of implanted boron in Si and silicide by multiple implants
(1998-07-01)
Chu, CH
;
Ho, KJ
;
Huang, CT
;
Shvu, SH
;
Lei, TF
To form an ultra-shallow p(+)-n junction by direct low energy BF2+ implantation is difficult. The channeling of the baron during implant and the transient enhanced diffusion of boron during annealing prohibit the tight control of the boron profile. Using the germanium preamorphization implant, the channeling probability of the boron is suppressed. However, the thickness of the pre-amorphized layer is crucial in alleviating the transient enhanced diffusion of boron. The excess point defects below the original amorphous/crystalline interface play a key role in enhancing the diffusion of boron. Introducing the carbon into the BF2+ implanted Si, the diffusion of the boron is retarded, Combining with the germanium pre-amorphization implant, low energy BF2+ implant and carbon implant, an ultra-shallow p(+)-n junction with a junction depth of about 70 nm is realized after rapid thermal annealing at 1050 degrees C, 10 s, Using the baron implanted TiSi2 as diffusion source to form an ultra-shallow p(+)-n junction is prohibited by the trapping of boron inside the TiSi2. The fabrication of high quality p(+)-n junction using this technique is difficult to achieve. Incorporation of germanium into the baron containing TiSi2, the diffusion of boron inside the TiSi2 is enhanced. Boron easily out-diffuses from the TiSi2 layer into the Si substrate and forms a high quality p+-n shallow junction. Manipulating the diffusion behavior of implanted boron in the Si and TiSi2 could be achieved by the multiple implants of germanium and carbon. The chemical interaction of co-implanted ions with the boron is the key to control the baron profile inside the silicon. (C) 1998 Elsevier Science S.A. All rights reserved.
Improvement of reliability of metal-oxide semiconductor field-effect transistors with N2O nitrided gate oxide and N2O polysilicon gate reoxidation
(1998-10-01)
Lai, CS
;
Chao, TS
;
Lei, TF
;
Lee, CL
;
Huang, TY
A systematic study of the impact of the reliability of metal-oxide semiconductor field-effect transistors (MOSFETs) with N2O nitrided gate oxides and N2O poly-reoxidation was conducted. The improvements include hot carrier immunity, suppression of reverse short channel effect and suppression of plasma-induced degradation. These improvements are due to nitrogen incorporation at the oxide/Si-substrate interface. All data presented in this study involve substantially low thermal budget (850 degrees C), making this N2O-related technology extremely attractive and promising for future scaled devices.
Improvement of ultra-thin 3.3 nm thick oxide for co-salicide process using NF3 annealed poly-gate
(1999-04-01)
Chang, TY
;
Lei, TF
;
Chao, TS
;
Huang, CT
;
Chen, SK
To get high quality ultra-thin oxide is very important and difficult for IC industry now. Using NF3 annealed poly-Si gate to improve gate oxide integrity is described. However, reducing fate, source and drain parasitic resistance with gate lengths down to 0.2 mu m is another key point. Co-salicide process can successfully reduce the gate resistance even for a gate length of 0.075 mu m. Although, Co-salicide process has a leakage problem. Using NF3 annealing to prevent Co diffusing into gate oxide is described too. Results show that the optimal NF3 annealing significantly improves electrical characteristics of ultra-thin oxide and Co-salicide process in terms of leakage current and breakdown field, as compared to the samples without NF3 annealing.
Enhancement of integrity of polysilicon oxide by using a combination of N2O nitridation and CMP process
(1999-05-01)
Lei, TF
;
Chen, JH
;
Wang, MF
;
Chao, TS
;
電子工程學系及電子研究所
This work prepares and demonstrates, for the first time, a high-quality polysilicon oxide, by combining N2O nitridation and Chemical Mechanical Polishing (CMP) process. Our results demonstrate that capacitors with this process have an improved Q(bd) (charge-to-breakdown) due to the planar surface and more concentrated nitrogen at the interface of polysilicon oxide.
A novel Si-B diffusion source for p(+)-poly-Si gate
(1999-10-01)
Chao, TS
;
Kuo, CP
;
Chen, TP
;
Lei, TF
;
電子工程學系及電子研究所
In this paper, we report a novel Si-B diffusion source for p(+)-polySi gate p-metal oxide-semiconductor field effect transistors (pMOSFETs). It is found that boron penetration can br effectively suppressed using this process. All the electrical properties of the MOS capacitors are significantly improved over the conventional BF2+ or B+-implanted samples. This process is very promising for fabrication of future surface-channel p-MOSFETs. (C) 1999 The Electrochemical Society. S0013-4651(99)03-017-7. All rights reserved.
Improvement of junction leakage of nickel silicided junction by a Ti-capping layer
(1999-11-01)
Hou, TH
;
Lei, TF
;
Chao, TS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel NiSi process with a thin Ti-cap layer is proposed, for the first time, to improve the leakage problem of Ni-silicided junction, The Ti-cap samples exhibit a very low leakage current density about 1 x 10 A/cm(2) after 600 degrees C annealing, which is one order of magnitude reduction comparing with uncapped samples. From Anger analyzes, it is found that this significant improvement results from suppression of the oxidation of the Ni-silicide during the thermal annealing process.
Low contact resistance of poly-plug structure by in-situ HF-vapour cleaning
(2000-04-13)
Chen, JH
;
Lei, TF
;
Chao, TS
;
Su, TP
;
Huang, SJ
A low contact-resistance poly-plug structure realised by in-situ HF-vapour cleaning in a clustered tool is described. The native oxide in the contact area can be efficiently removed by the combination of an HF-dipping and in-situ HF-vapour cleaning process, resulting in a low specific contact resistance.

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