<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css">

學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

Filters

2002 - 20065

Settings

🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Lei, TFSubject: search.filters.subject.reliability

Search Results

Now showing 1 - 5 of 5
  • Thumbnail Image
    Item type:Item,
    Thin oxides grown on disilane-based polysilicon
    (2002-06-01)
    Lee, JW
    ;
    Lei, TF
    ;
    Lee, CL
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This report describes the thin oxide (<10 nm) thermally grown on polysilicon film, which was prepared by disilane (Si2H6) chemical vapor deposition. In comparison with the thin oxide grown on conventional silane (SiH4) polysilicon film, the prepared oxides have lower leakage current,;. a lower electron trapping rate and a larger charge to breakdown distribution. These good properties are attributed to the smooth surface of the disilane poly-I film. This film is suitable for use as the interpoly oxide of electrically-erasable programmable read only memory.
  • Thumbnail Image
    Item type:Item,
    A novel process-compatible fluorination technique with electrical characteristic improvements of poly-Si TFTs
    (2005-06-01)
    Wang, SD
    ;
    Lo, WH
    ;
    Chang, TY
    ;
    Lei, TF
    ;
    電子工程學系及電子研究所
    A process-compatible fluorine passivation technique of poly-Si thin-film transistors (TFTs) was demonstrated by employing a novel CF4 plasma treatment. Introducing fluorine atoms into poly-Si films can effectively passivate the trap states near the SiO2/poly-Si interface. With fluorine incorporation, the electrical characteristics of poly-Si TFTs can be significantly improved including a steeper subthreshold slope, smaller threshold voltage, lower leakage current, higher field-effect mobility, and better On/Off current ratio. Furthermore, the CF4 plasma treatment also improves the reliability of poly-Si TFTs with respect to hot-carrier stress, which is due to the formation of strong Si-F bonds.
  • Thumbnail Image
    Item type:Item,
    Performance and reliability of poly-Si TFTs on FSG buffer layer
    (2005-07-01)
    De Wang, S
    ;
    Chang, TY
    ;
    Chien, CH
    ;
    Lo, WH
    ;
    Sang, JY
    A novel and process-compatible scheme for fabricating poly-Si thin-film transistors (TFTs) on an FSG buffer layer was proposed and demonstrated. Experimental results reveal that remarkably improved device performance and uniformity can be achieved with appropriate fluorine concentration. The poly-Si TFTs fabricated on FSG layers have a higher on-current, a lower leakage current, and a higher field-effect mobility compared with the conventional poly-Si TFTs. Furthermore, the incorporation of fluorine also increased the reliability of poly-Si TFTs against hot carrier stressing, which is attributed to the formation of Si-F bonds.
  • Thumbnail Image
    Item type:Item,
    Characterization of polysilicon thin-film transistors with asymmetric source/drain implantation
    (2005-08-01)
    Shieh, MS
    ;
    Lin, YJ
    ;
    Yu, CM
    ;
    Lei, TF
    ;
    電子工程學系及電子研究所
    The effect of asymmetry tilt angle ion implantation on polysilicon thin-film transistors (TFTs) device characteristics are investigated. This asymmetric source/drain (S/D) TFTs structure exhibits low leakage current and suppressed kink effect due to the relief of higher electric field near the drain junction side. It is shown that the optimal implantation tilt angle is 30 degrees in our annealing condition. And the anomalous off-state current is more than two orders of magnitude lower than that of the conventional TFTs. By well controlled the LDD region, this structure can act as a conventional structure in the on-state and the turn-on current will not be degraded. Besides, the device under severe hot carrier bias stress shows better hot carrier endurance. (c) 2005 Elsevier B.V. All rights reserved.
  • Thumbnail Image
    Item type:Item,
    Investigation of DC hot-carrier degradation at elevated temperatures for n-channel metal-oxide-semiconductor field-effect-transistor of 0.13 mu m technology
    (2006-04-01)
    Lin, JC
    ;
    Chen, SY
    ;
    Chen, HW
    ;
    Jhou, ZW
    ;
    Lin, HC
    In this study, n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) having 20 and 32 angstrom gate oxide thicknesses of 0.13 mu m technology were used to investigate DC hot-carrier reliability at elevated temperatures up to 125 degrees C. The research also focused on the degradation of analog properties after hot-carrier injection. On the basis of the results of experiments, the hot-carrier degradation of I-d.op (drain current defined on the basis of analog applications) is found to be the worst case among those of three types of drain current from room temperature to 125 degrees C. This result should provide valuable insight to analog circuit designers. As to the reverse temperature effect, the substrate current (I-b) commonly accepted as the parameter for,monitoring the drain-avalanche-hot-carrier (DAHC) effect should be modified since the drain current (I-d) degradation and I-b variations versus temperature have different trends. For the devices having a gate oxide thinner than 20 angstrom, we suggest that the worst condition in considering hot-carrier reliability should be placed at elevated temperatures.