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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Li, YimingSubject: search.filters.subject.FinFET

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Now showing 1 - 7 of 7
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    Exploration of Inter-Die Bulk Fin-Typed Field Effect Transistor Process Variation for Reduction of Device Variability
    (2016-06)
    Su, Ping-Hsun
    ;
    Li, Yiming
    ;
    交大名義發表
    ;
    傳播研究所
    ;
    電機學院
    This work first reports a novel exploration technique to systematically prioritize key fabrication in-line process parameters of 16-nm high-k metal gate (HKMG) bulk FinFET to reduce device\'s die-to-die variation. To extract hidden correlations and reduce decision variables among the complex in-line process parameters, a data mining technique is employed to highlight and group associated parameters. To correlate the measured data with the distribution of physical dimension of devices for all in-line processes, a sensitivity analysis is then performed. Because the variability of current process deeply affects the next process, so the sequence of fabrication process is further added into the analyzing procedure to increase the searching efficiency. The source of variation of the initial process can be monitored and traced by the proposed methodology. The result of this study indicates that the gate spacer is a key process factor and will determine the uniformity of process including, such as the source-and-drain proximity, and the depth, lateral offset and overlap of sequential doping implants. The ranked key in-line process parameters can be used to optimize process and minimize the device variability of 16-nm HKMG bulk FinFET devices.
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    Mobility model extraction for surface roughness of SiGe along (110) and (100) Orientations in HKMG bulk FinFET devices
    (2013-09-01)
    Chen, Chien-Hung
    ;
    Li, Yiming
    ;
    Chen, Chieh-Yang
    ;
    Chen, Yu-Yu
    ;
    Hsu, Sheng-Chia
    In this work, the FinFET HKMG MOS devices are fabricated on silicon wafer with p-substrate. The interface roughness between the SiGe and SiO2 is experimentally extracted and calculated as a function of root mean square by analysis of high resolution transmission electron microscopy. The surface-roughness dependent mobility model is then incorporated into device simulation to study the mobility of SiGe along (110) and (100) orientations of the devices. We further analyze four devices with different surface roughness along (100) and (100) orientations to demonstrate the influence of surface roughness on the total effective mobility. (C) 2013 Elsevier B.V. All rights reserved.
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    Threshold Voltage Fluctuation in 16-nm-Gate FinFETs Induced by Random Work Function of Nanosized Metal Grain
    (2012-06-01)
    Li, Yiming
    ;
    Cheng, Hui-Wen
    ;
    Hwang, Chi-Hong
    ;
    電機資訊學士班
    ;
    Undergraduate Honors Program of Electrical Engineering and Computer Science
    The random work-function (WK) induced threshold voltage fluctuation (sigma V-th) in 16 nm Titanium Nitride (TiN) metal-gate fin-type field effect transistors (FinFETs) is explored and modeled by using an experimentally validated Monte Carlo simulation approach. The influences of metal-grain size and device geometry aspect ratio on the random WK-induced sigma V-th are considered in the proposed equation analytically. The formula accounts for the inside of fluctuation and could be used for the assessment of effectiveness of suppression techniques.
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    Random Work Function Variation Induced Threshold Voltage Fluctuation in 16-nm Bulk FinFET Devices with High-kappa-Metal-Gate Material
    (2010)
    Cheng, Hui-Wen
    ;
    Li, Yiming
    ;
    傳播研究所
    ;
    Institute of Communication Studies
    The random work-function (WK) induced threshold voltage fluctuation (sigma Vth) in 16-nm TiN metal-gate fin-type field effect transistors (FinFETs) is explored and modeled by using an experimentally validated Monte Carlo simulation approach. The influences of metal-grain size and device geometry aspect ratio on the random WK-induced sigma Vth are studied analytically. The results of this study allow us to identify suitable materials for metal gate and to clarify reduction of the sigma Vth owing to WKF. Among four different gate materials, the titanium nitride possesses the smallest sigma Vth due to small size of metal grains.
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    Discrete Dopant Induced Electrical and Thermal Fluctuation in Nanoscale SOI FinFET
    (2007)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    Yu, Shao-Ming
    ;
    Huang, Hsuan-Ming
    ;
    電信工程研究所
    The International Roadmap for Semiconductors has forecasted a transition from conventional bulk device to silicon-on-insulator (SOI) one, and then to multiple-gate SOI for high-performance devices. Impact of the discrete-dopant number and discrete-dopant position on device characteristics is crucial for nanoscale semiconductor devices. In this paper, the discrete dopant induced electrical and thermal fluctuation of 16nm SOI FinFETs is for the first time explored. A three-dimensional atomistic" device simulation with quantum hydrodynamic equation is proposed and performed for electrical and thermal characteristics of the discrete dopant fluctuated SOI FinFETs. Discrete dopants are statistically positioned in the 3D channel region to study associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Effect of the discrete-dopant-number- and discrete-dopant-position-induced fluctuations on device characteristic including variations of the lattice and electron temperatures are advanced. The large-scale computational statistics study provides us an insight into the fluctuation of electrical and thermal characteristics and mechanism of immunity against fluctuation in SOI FinFETs.
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    Three-dimensional simulation of random-dopant-induced threshold voltage fluctuation in nanoscale Fin-typed field effect transistors
    (2007)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    Yu, Shao-Ming
    ;
    Huang, Hsuan-Ming
    ;
    資訊工程學系
    Nanoscale multiple-gate fin-typed field effect transistors (FinFETs) are promising candidates for next generation semiconductor devices. Impact of the discrete-dopant number and discrete-dopant position on device characteristics is crucial for nanoscale semiconductor devices. In this paper, we study the discrete-dopant-induced potential and threshold voltage fluctuations in 16nm triple-gate FinFET devices. Discrete dopants are statistically positioned into the three dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". It is found that the inhomogeneity of the potential induced by the discreteness of the channel dopants significantly disturbs device threshold voltage, and thus the device characteristics. This study provides an insight into the source of fluctuation and fluctuations induced by discrete dopants in ultra-small field effect transistors with vertical channel structures.
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    Numerical simulation of static noise margin for a six-transistor static random access memory cell with 32nm fin-typed field effect transistors
    (2007)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    Yu, Shao-Ming
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    We in this paper for the first time explore the static noise margin (SNM) of a six-transistor (6T) static random access memory (SRAM) cell with nanoscale silicon-on-insulator (SOI) fin-typed field effect transistors (FinFETs). The SNM is calculated with respect to the supply voltage, operating temperature, and cell ratio by performing a three-dimensional mixed-mode simulation. To include the quantum mechanical effect, the density-gradient equation is simultaneously solved in the coupled device and circuit equations. The standard deviation (sigma-(S N M)) of SNM versus device's channel length is computed, based upon the design of experiment and response surface methodology. Compared with the result of SNM for SRAM with 32nm planar metal-oxide-semiconductor field effect transistors, SRAM with SOI FinFETs quantitatively exhibits higher SNM and lower sigma-(S N M). Improvement of characteristics resulting from good channel controllability implies that SRAM cells fabricated with FinFETs continuously maintains cell stability in sub-32nm technology nodes.