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Now showing 1 - 10 of 275
  • Item type:Item,
    Design and Simulation of High Performance Lattice Matched Double Barrier Normally Off AlInGaN/GaN HEMTs
    (2020-01-01)
    Shrestha, Niraj Man
    ;
    Li, Yiming
    ;
    Chen, Chao-Hsuan
    ;
    Sanyal, Indraneel
    ;
    Tarng, Jenn-Hawn
    A novel lattice matched double barrier Al0.72In0.16Ga0.12N/Al0.18In0.04Ga0.78N/GaN normally-off high electron mobility transistor (HEMT) is designed and simulated by solving a set of thermodynamic transport equations. Using the experimentally calibrated physical models with bearing mobility degradation by surface roughness in account, the recess gate and double barrier of the proposed device achieves a maximum drain current density (I-D,I-max) of 1149 mA/mm and a maximum transconductance (g(m,max)) of 358 mS/mm with a positive threshold voltage (Vth) of 0.2 V. The small polarization charge of first barrier is responsible for positive Vth. I-DS,I-max in the double barrier HEMT at high gate bias condition is due to injection of electrons from upper 2DEG which is almost impossible at lower gate voltage because of insufficient energy to cross the barrier. The injection of electrons is further supported by the second peak in the g(m) curve at low gate bias V-G = 1V. The outcome of this study suggests that the proposed device will be beneficial for high-frequency and high-power electronic applications.
  • Item type:Item,
    Statistical Prediction of Nanosized-Metal-Grain-Induced Threshold-Voltage Variability for 3D Vertically Stacked Silicon Gate-All-Around Nanowiren-MOSFETs
    (1970-01-01)
    Sung, Wen-Li
    ;
    Li, Yiming
    ;
    交大名義發表
    ;
    電機工程學系
    ;
    電信工程研究所
    In this study, we present a statistically accurate model to predict the threshold-voltage variability (sigma V-th) efficiently for three-dimensional (3D) vertically stacked silicon (Si) gate-all-around (GAA) nanowire (NW)n-MOSFETs with multi-channels. The statistical results indicate that the sigma V(th)decreases exponentially by increasing metal grain number (MGN), which is unitless. Additionally, the magnitude of sigma V(th)was calculated for various MGNs, which joins the normality test with Anderson-Darling test. Therefore, the model with MGN can be implemented by nonlinear regression with a regression coefficient of approximately one. From this model and the perspective of process, more 3D vertically stacked channels can reduce the value and sensitivity of sigma V-th. This study provides useful information from statistics to explain the experiment results for 3D vertically stacked Si GAA NWn-MOSFETs with multi-channels.
  • Item type:Item,
    Effects of random number and location of the nanosized metal grains on the threshold voltage variability of silicon gate-all-around nanowiren-type metal-oxide-semiconductor field-effect transistors
    (1970-01-01)
    Sung, Wen-Li
    ;
    Li, Yiming
    ;
    交大名義發表
    ;
    電機工程學系
    ;
    電信工程研究所
    In this study, the effect of the metal grain number (MGN) and metal grain location (MGL) with a low/high work function (WK) on the variability of the threshold voltage (sigma V-th) of silicon gate-all-around nanowiren-type metal-oxide-semiconductor field-effect transistors was examined by using an experimentally validated cuboid grain method. For the effect of the MGN,sigma V(th)induced by WK fluctuations strongly depended on the MGN for the same metal-gate area. For the effect of the MGL, metal grains with a low WK near the source (S) side are crucial for the magnitude of sigma V-th. Therefore, for the weighted superposition of the WK with each metal grain, the number of metal grains with a low WK near theSside may alter the distribution ofV(th)and dominate the magnitude of sigma V-th.
  • Item type:Item,
    Numerical Simulation of Thermal Conductivity of SiNW-SiGe0.3 Composite for Thermoelectric Applications
    (2020-05-01)
    Lee, Ming-Yi
    ;
    Li, Yiming
    ;
    Chuang, Min-Hui
    ;
    Ohori, Daisuke
    ;
    Samukawa, Seiji
    The electron band structure and phonon energy dispersion of the silicon nanowires (SiNWs) embedded in SiGe0.3 (SiNW-SiGe0.3 composite) are simulated by using the effective mass Schrodinger equation and the elastodynamic wave equation, respectively. Then, the TE properties of the SiNW-SiGe0.3 composite are investigated by the Landauer approach. The simulation shows the contribution from electrons/holes on both electrical conductance and thermal conductance increases few times by introducing SiNWs, but on the other hand, lattice thermal conductance reduces around two orders. These results are consistent with the experimental measurement and indicates that much lower lattice thermal conductance dominates the TE performance of the SiNW-SiGe0.3 composite.
  • Item type:Item,
    Effects of a dual spacer on electrical characteristics and random telegraph noise of gate-all-around silicon nanowire p-type metal-oxide-semiconductor field-effect transistors
    (2020-04-01)
    Kola, Sekhar Reddy
    ;
    Li, Yiming
    ;
    Thoti, Narasimhulu
    ;
    交大名義發表
    ;
    電機工程學系
    Using a dual spacer consisting of 50% SiO2 and 50% HfO2, the ratio of the on-state current/the off-state current in the order of 10(6) is achieved for the explored devices. Based on the experimentally validated simulation, the result indicates that the variation of gate-capacitance is significant owing to the sizeable parasitic capacitance resulting from the spacer. The role of the spacer acts as the parallel plate capacitor, the amount of gate capacitance will be increased largely with the HfO2 due to its high parasitic capacitance. For the devices without any spacers, induced by a donor-type single charge trap (SCT), the statistically calculated highest amplitude of random telegraph noise (RTN) is 2.32%. It occurs when the SCT locates in the middle of the channel due to the high occurrence of capture and emission for SCT under low gate voltage. Notably, for devices with considerable spacers, the RTN can be significantly suppressed (<= 1%). (C) 2020 The Japan Society of Applied Physics
  • Item type:Item,
    Low resistive InGaN film grown by metalorganic chemical vapor deposition
    (2020-01-01)
    Shrestha, Niraj Man
    ;
    Chauhan, Prerna
    ;
    Wong, Yuen-Yee
    ;
    Li, Yiming
    ;
    Samukawa, Seiji
    Indium gallium nitride (InGaN) samples were grown on sapphire substrate with low temperature GaN buffer by metalorganic chemical vapor deposition (MOCVD) under varying growth conditions, such as temperature, pressure and ammonia flow. Although high indium composition is considered as indispensable parameter for sheet carrier concentration (n(s)) and low sheet resistance (R-s), our outcomes disclose that higher indium composition in InGaN film doesn't always have high n(s) and low R-s. Acceptor nature of carbon related defects, a major trapping sites for electrons, plays a crucial role to limit the carrier concentrations in the InGaN specially grown at low pressure, low temperature and low ammonia flow. Furthermore, study of metal contacts deposited on the grown samples by transmission line method (TLM) shows that carrier concentration is the most important factor to obtain low contact resistance. The measured contact resistance for the sample with 4.5x 10(16) cm(2) carrier concentration is 0.13 Omm which is among the lowest contact resistance for GaN based materials grown by MOCVD. This proves that the use of InGaN in source and drain contact region can surpassingly reduce contact resistance and significantly improve device performance of AlGaN/GaN device.
  • Item type:Item,
    Atomic layer defect-free etching for germanium using HBr neutral beam
    (2019-09-01)
    Fujii, Takuya
    ;
    Ohori, Daisuke
    ;
    Noda, Shuichi
    ;
    Tanimoto, Yosuke
    ;
    Sato, Daisuke
    The authors developed extremely selective etching for making an atomically flat, defect-free germanium fin (Ge Fin) structure. The etching uses a hydrogen bromide (HBr) neutral beam (NB), and they investigated the etching reaction differences between the HBr NB and a Cl-2 NB. No sidewall etching by HBr NB occurred at 90 degrees C, although that by Cl-2 NB occurred at more than 90 degrees C. This was due to the different boiling points of GeBr4 and GeCl4 as the reacted layer was formed by NB irradiation on the Ge surface. As a result, the Ge sidewall etching by Cl-2 NB occurred above 90 degrees C, whereas that by HBr NB did not occur at 90 degrees C. Additionally, nonvolatile bromide protected layers, such as GeBr4 and SiBrxOy, were deposited on the Ge sidewall and the SiO2 top surface in case of using HBr, respectively. Then, the authors succeeded in fabricating the atomically flat, defect-free Ge Fin structure with the extremely selective HBr NB etching. This result shows that HBr NB can more precisely achieve sub-10-nm scale atomic layer Ge etching for 3D Fin-type MOSFETs.
  • Item type:Item,
    Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits
    (2019-05-01)
    Li, Yiming
    ;
    Chen, Chieh-Yang
    ;
    Chuang, Min-Hui
    ;
    Chao, Pei-Jung
    ;
    電機工程學系
    In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal-oxide-semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device's nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device-circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation.
  • Item type:Item,
    Electrical Characteristic of AlGaN/GaN High-Electron-Mobility Transistors With Recess Gate Structure
    (2019-04-01)
    Shrestha, Niraj Man
    ;
    Li, Yiming
    ;
    Suemitsu, Tetsuya
    ;
    Samukawa, Seiji
    ;
    交大名義發表
    AlGaN/GaN high-electron-mobility transistors (HEMTs) with nonrecess and recess gates are simulated by solving a set of drift-diffusion equations for electrostatic potential and electron-hole concentrations with self-heating model. The approach is first calibrated for both HEMT devices with experimentally measured data, to provide the best accuracy of the simulation. Recess gate device suffers from high potential to the channel, increased parasitic resistances, and deep level traps in barrier due to surface roughness. In addition, selective thinning of the barrier and increase parasitic resistance results in 17% reduction on the carrier concentration. The carrier mobility degradation due to surface roughness and electron velocity lessen due to high electric field result shrinkage of current density with considerable shift of the threshold voltage toward positive value. Even though transconductance does not seems to be remarkably changed for 3-nm recess gate, its value increases on deeper recess. This paper reveals that surface roughness is crucial issue that has dominant role behind the low current density in the recess gate structure. The detail physical understanding of the recess technology will be helpful to minimize the performance deterioration of the explored devices.
  • Item type:Item,
    Tuning of the electron g factor in defect-free GaAs nanodisks
    (2015-12-15)
    Yang, Li-Wei
    ;
    Tsai, Yi-Chia
    ;
    Li, Yiming
    ;
    Higo, Aiko
    ;
    Murayama, Akihiro
    We theoretically study the impact of changes in surroundings on the electron ground-state effective g factor in defect-free GaAs/AlGaAs nanodisks. To perform the study, we formulate and deploy a computational efficient full three-dimensional model to describe the effective g-factor tensor in semiconductor nano-objects of complex geometry and material content. This model is based on an effective 2 x 2 conduction-band Hamiltonian which includes the Rashba and Dresselhaus spin-orbit couplings. The description is suited to clarify the important question of the controllability of the electron effective g factor in semiconductor nano-objects. The results of this theoretical study suggest that in the defect-free GaAs/AlGaAs nanodisks, the effective g factor can be tuned within a wide range by proper design of the nanodisk environment. The zz components of the electron effective g-factor tensor obtained in our simulation are in good agreement with some recent experimental observations.