🏛️國立陽明交通大學機構典藏

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ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications
(2017-01-01)
Ker, Ming-Don
;
Lin, Chun-Yu
;
Wu, Yi-Han
;
Wang, Wen-Tai
;
電子工程學系及電子研究所
On-chip electrostatic discharge (ESD) protection design with low-leakage consideration for the silicon chips of IoT applications is presented. The proposed ESD protection design uses the fast turn-on silicon-controlled rectifier (SCR) device to implement the power-rail ESD clamp circuit. Experimental results verified in TSMC 28nm CMOS process have shown that the proposed design has advantages of low leakage current (2 similar to 3nA), low trigger voltage (similar to 2V), high ESD robustness (>8kV), and free to latchup issue.
Study on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technology
(2015)
Lin, Chun-Yu
;
Ker, Ming-Dou
;
Chang, Pin-Hsin
;
Wang, Wen-Tai
;
電子工程學系及電子研究所
To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.
Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-mu m CMOS process
(2015-11-01)
Lin, Chun-Yu
;
Chiu, Yan-Lian
;
生醫電子轉譯研究中心
;
Biomedical Electronics Translational Research Center
In these decades, integrated circuits for biomedical electronics applications have been designed and implemented in CMOS technologies. In order to be safely used by human, all microelectronic products must meet the reliability specifications. Therefore, electrostatic discharge (ESD) must be taken into consideration. To protect the biomedical integrated circuits in CMOS technologies from ESD damage, a dual-directional silicon-controlled rectifier (DDSCR) device was presented in this work. Experimental results show that the DDSCR has the advantages of high ESD robustness, low leakage, large swing tolerance, and good latchup immunity. The DDSCR was suitable for ESD protection in biomedical integrated circuits. (C) 2015 Elsevier Ltd. All rights reserved.
Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process
(2013-11-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To protect a 40-Gb/s transceiver from electrostatic discharge (ESD) damages, a robust ESD protection design has been proposed and realized in a 65-nm CMOS process. In this paper, diodes are used for ESD protection and inductors are used for high-speed performance fine tuning. Experimental results of the test circuits have been successfully verified, including highspeed performances and ESD robustness. The proposed design has been further applied to a 40-Gb/s current-mode logic (CML) buffer. Verified in silicon chip, the 40-Gb/s CML buffer with the proposed design can achieve good high-speed performance and high ESD robustness.
Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits
(2013-03-01)
Chu, Li-Wei
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
光電工程學系
To effectively protect the millimeter-wave (MMW) circuits in nanoscale CMOS technology from electrostatic discharge (ESD) damages, a dual-band ESD protection cell for 24-/60-GHz ESD protection is presented in this paper. The proposed ESD protection cell consisted of a diode, a silicon-controlled rectifier, a PMOS, and two inductors. To verify the dual-band characteristics and ESD robustness, the proposed ESD protection circuit had been applied to a 24-/60-GHz low-noise amplifier (LNA). The measurement results showed over-2-kV human-body-model ESD robustness with little performance degradation on LNA. The proposed dual-band ESD protection cell was suitable for circuit designers for them to easily apply ESD protection in the dual-band MMW circuits.
Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology
(2012-09-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, an on-chip ESD protection design must be included in the RF circuits. As the RF circuits operate in the higher frequency band, the parasitic effect from ESD protection circuit must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier with less RF performance degradation, two new ESD protection circuits were studied in a 65-nm CMOS process. Such compact ESD protection circuits have been successfully verified in silicon chip to achieve the 2-kV human-body-model ESD robustness with the low insertion loss in small layout area. With the better performances, the proposed ESD protection circuits were very suitable for V-band RF ESD protection.

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