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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Author: search.filters.author.Lin, Chun-YuSubject: search.filters.subject.Diode

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Now showing 1 - 5 of 5
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    On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology
    (2017-10-01)
    Chen, Jie-Ting
    ;
    Lin, Chun-Yu
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology.
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    ESD Protection Design for Wideband RF Applications in 65-nm CMOS Process
    (2014)
    Chu, Li-Wei
    ;
    Lin, Chun-Yu
    ;
    Ker, Ming-Dou
    ;
    Song, Ming-Hsiang
    ;
    Tseng, Jen-Chou
    All wireless communication products must meet the reliability specifications during mass production. To prevent from electrostatic discharge (ESD) damages, the ESD protection designs must be added at all input/output pads in chip. Some ESD protection designs with low parasitic capacitance for radio-frequency (RF) applications are reviewed in this paper. Besides, a novel ESD protection design is proposed and realized in a 65nm CMOS process to protect the wideband RF circuits. In this work, diodes are used for ESD protection and inductors are used for high-frequency performance fine tuning. Experimental results of the test circuits have been successfully verified.
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    Improving ESD Robustness of Stacked Diodes with Embedded SCR for RF Applications in 65-nm CMOS
    (2014)
    Lin, Chun-Yu
    ;
    Fan, Mei-Lian
    ;
    Ker, Ming-Dou
    ;
    Chu, Li-Wei
    ;
    Tseng, Jen-Chou
    To protect the radio-frequency (RF) integrated circuits from the electrostatic discharge (ESD) damage in nanoscale CMOS process, the ESD protection circuit must be carefully designed. In this work, stacked diodes with embedded silicon-controlled rectifier (SCR) to improve ESD robustness was proposed for RF applications. Experimental results in 65-nm CMOS process show that the proposed design can achieve low parasitic capacitance, low turn-on resistance, and high ESD robustness.
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    Area-Efficient and Low-Leakage Diode String for On-Chip ESD Protection
    (2016-02-01)
    Lin, Chun-Yu
    ;
    Wu, Po-Han
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Diode string was used as the effective on-chip electrostatic discharge (ESD) protection device. To reduce the leakage current and the layout area, an area-efficient and low-leakage diode string is proposed in this paper. The standard steps of P- implantation and silicide blocking in CMOS process are used in this design to realize the proposed diode string with stacked P-/N+ diodes. The test devices of the proposed design have successfully been verified in the silicon chip. With the high ESD robustness, low leakage current, and small layout area, the proposed diode string can be a better solution for on-chip ESD protection applications.
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    Optimization on Layout Style of Diode Stackup for On-Chip ESD Protection
    (2014-06-01)
    Lin, Chun-Yu
    ;
    Fan, Mei-Lian
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than V-DD or lower than V-SS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.