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Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High-Speed Digital Application in 16-nm FinFET Process
(2020-07-01)
Chang, Rong-Kun
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The FinFET architecture has widely been used in the digital circuit application, due to the good short channel effect control and driving current boost. However, the worse thermal dispassion and smaller effective silicon volume would cause the significant impacts during the circuits under electrostatic discharge (ESD) event. Thus, the ESD protection device should be installed into the high-speed digital circuit to enhance the ESD robustness. To avoid the effect of circuit performance, the parasitic capacitance of ESD device must be as low as possible. In this article, two types of Fin-diode-triggered rotated silicon-controlled rectifier (SCR) with dual ESD current path have been proposed and verified in a 16-nm FinFET CMOS process. The proposed devices have better current-handling capability, sufficiently low parasitic, compact layout area, and low leakage current.
ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications
(2017-01-01)
Ker, Ming-Don
;
Lin, Chun-Yu
;
Wu, Yi-Han
;
Wang, Wen-Tai
;
電子工程學系及電子研究所
On-chip electrostatic discharge (ESD) protection design with low-leakage consideration for the silicon chips of IoT applications is presented. The proposed ESD protection design uses the fast turn-on silicon-controlled rectifier (SCR) device to implement the power-rail ESD clamp circuit. Experimental results verified in TSMC 28nm CMOS process have shown that the proposed design has advantages of low leakage current (2 similar to 3nA), low trigger voltage (similar to 2V), high ESD robustness (>8kV), and free to latchup issue.
On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology
(2017-10-01)
Chen, Jie-Ting
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology.
Study on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technology
(2015)
Lin, Chun-Yu
;
Ker, Ming-Dou
;
Chang, Pin-Hsin
;
Wang, Wen-Tai
;
電子工程學系及電子研究所
To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.
Improving ESD Robustness of Stacked Diodes with Embedded SCR for RF Applications in 65-nm CMOS
(2014)
Lin, Chun-Yu
;
Fan, Mei-Lian
;
Ker, Ming-Dou
;
Chu, Li-Wei
;
Tseng, Jen-Chou
To protect the radio-frequency (RF) integrated circuits from the electrostatic discharge (ESD) damage in nanoscale CMOS process, the ESD protection circuit must be carefully designed. In this work, stacked diodes with embedded silicon-controlled rectifier (SCR) to improve ESD robustness was proposed for RF applications. Experimental results in 65-nm CMOS process show that the proposed design can achieve low parasitic capacitance, low turn-on resistance, and high ESD robustness.
Area-Efficient and Low-Leakage Diode String for On-Chip ESD Protection
(2016-02-01)
Lin, Chun-Yu
;
Wu, Po-Han
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Diode string was used as the effective on-chip electrostatic discharge (ESD) protection device. To reduce the leakage current and the layout area, an area-efficient and low-leakage diode string is proposed in this paper. The standard steps of P- implantation and silicide blocking in CMOS process are used in this design to realize the proposed diode string with stacked P-/N+ diodes. The test devices of the proposed design have successfully been verified in the silicon chip. With the high ESD robustness, low leakage current, and small layout area, the proposed diode string can be a better solution for on-chip ESD protection applications.
Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process
(2014-11-01)
Lin, Chun-Yu
;
Fan, Mei-Lian
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The pin-to-pin electrostatic discharge (ESD) issue for a differential low-noise amplifier (LNA) was studied in this work. A new design of ESD protection diodes with an embedded silicon-controlled rectifier (SCR) was proposed to protect the gigahertz differential LNA. The proposed ESD protection design was modified from the conventional ESD protection design without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad so the pin-to-pin ESD robustness can be improved. This design had been verified in a 65-nm CMOS process. Besides, this design had been further applied to a 24-GHz LNA in the same 65-nm CMOS process. Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.
Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
(2008-05-01)
Ker, Ming-Dou
;
Lin, Chun-Yu
;
電機學院
;
College of Electrical and Computer Engineering
The silicon-controlled rectifier (SCR) has been used as an effective on-chip electrostatic discharge (ESD) protection device in CMOS technology due to the highest ESD robustness in nanoscale integrated circuits (10). In this study, the SCR realized in a waffle layout structure is proposed to improve ESD current distribution efficiency for ESD protection and to reduce the parasitic capacitance. The waffle layout structure of the SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs. Besides, the desired current to trigger on the SCR device with a waffle layout structure and its turn-on time has also been investigated in a silicon chip.
Self-Matched ESD Cell in CMOS Technology for 60-GHz Broadband RF Applications
(2010)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
Lu, Tse-Hua
;
Hung, Ping-Fang
A self-matched ESD cell library has been implemented in a commercial sub-100nm CMOS process for 60-GHz broadband RF applications. This ESD cell library has reached the 50-Omega input/output matching to reduce the design complexity for RF circuit designer and to provide suitable electrostatic discharge (ESD) protection. Experimental results of this ESD cell library have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. This self-matched ESD cell library is easily to be used for ESD protection design in the 60-GHz broadband RF applications.
Optimization on Layout Style of Diode Stackup for On-Chip ESD Protection
(2014-06-01)
Lin, Chun-Yu
;
Fan, Mei-Lian
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than V-DD or lower than V-SS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.

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