學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Search Results

Now showing 1 - 10 of 14

Ohmic Contacts with low contact resistance for GaN HEMTs
(2019-01-01)
Chang, Edward Yi
;
Lin, Yen-Ku
;
材料科學與工程學系
;
電子工程學系及電子研究所
;
國際半導體學院
GaN-based high electron mobility transistor (HEMT) is a promising candidate for high-frequency and high-power applications due to its outstanding material properties, such as high electric breakdown field and high peak electron drift velocity. A low contact resistance (R-c) contact is essential for the device performance including output power, power efficiency, frequency response and noise performances. To obtain low contact resistances, several studies using different metallization schemes have been demonstrated. A standard Ti/Al/Ni/Au metal stack is a conventional ohmic contact of GaN HEMTs. Ti reacts with AlGaN to form TiN, which results in the creation of nitrogen vacancies which act as donors in AlGaN layers. The resultant N-type doped AlGaN and the conductive TiN facilitate tunneling mechanism of carriers at the interface.
InGaAs Junctionless FinFETs With Self-Aligned Ni-InGaAs S/D
(2018-01-01)
Chang, Po-Chun
;
Hsiao, Chih-Jen
;
Lumbantoruan, Franky Juanda
;
Wu, Chia-Hsun
;
Lin, Yen-Ku
In this paper, the InGaAs junctionless (JL) FinFET with notable electrical performance is demonstrated. The device with W-fin down to 20 nm, EOT of 2.1 nm, and L-G = 60 nm shows high I-ON = 188 mu A/mu m at V-DD = 0.5 V and I-OFF = 100 nA/mu m, I-ON/I-OFF = 5 x 10(5), DIBL = 106 mV/V and SS = 96 mV/dec. The device also exhibits a decent extrinsic transconductance (G(m)) of 1142 mu S/mu m at V-DS of 0.5 V. This high performance is attributed to the moderate doping concentration to ensure the channel carriers could be effectively depleted and the low R-SD realized by self-aligned Ni-InGaAs alloy S/D. Furthermore, we also examine the temperature dependence of the main electrical parameters of the JL transistor.
A versatile low-resistance ohmic contact process with ohmic recess and low-temperature annealing for GaN HEMTs
(2018-09-01)
Lin, Yen-Ku
;
Bergsten, Johan
;
Leong, Hector
;
Malmros, Anna
;
Chen, Jr-Tai
Deeply recessed ohmic contacts for GaN-based high electron mobility transistors (HEMTs) are demonstrated. It is shown that low-resistance ohmic contacts can be achieved with recessing beyond the AlGaN Schottky barrier where the ohmic contacts are formed on the sidewall of the recess. This makes the process versatile and relatively insensitive to the exact recess depth. The ohmic contact is based on a gold-free metallization scheme consisting of a Ta/Al/Ta metal stack requiring a low-temperature annealing. Important parameters for this type of ohmic contact process include the metal coverage, slope of the etched sidewall, bottom Ta-layer thickness, as well as annealing temperature and duration. The optimized contact resistance is as low as 0.24 Omega mm after annealing at 575 degrees C. Moreover, this sidewall contact approach was successfully implemented on different epitaxial heterostructures with different AlGaN barrier thickness as well as with and without AlN exclusion layer. All the samples exhibited excellent contact resistances in a wide range of recess depths. The Ta-based, sidewall ohmic contact process is a promising method for forming an ohmic contact on a wide range of GaN HEMT epitaxial designs.
Normally-OFF GaN MIS-HEMT With F- Doped Gate Insulator Using Standard Ion Implantation
(2018-01-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
;
Quang Ho Luc
;
Hsu, Ching-Yi
;
Hsieh, Ting-En
A normally-OFF GaN metal-insulator-gate high electron mobility transistors with fluorine doped gate insulator has been fabricated using standard ion implantation technique. Fluorine ions with negative charges were doped lightly into both the gate insulator and the partially recessed barrier layer, resulting in high positive threshold voltage (V-th) for the device, meanwhile preserving low ON-resistance. Compared to the fluorine-free and recess-free device, only about 16% increase of ON-resistance was observed for the F- doped devices. The fabricated F- doped device exhibits a threshold voltage of +0.68 V at I-Ds = 5 mu A/mm, a current density of 620 mA/mm, an OFF-state breakdown voltage of 800 V, and high ON/OFF current ratio of 10(10). For thermal stability consideration of fluorine dopant, the V-th-thermal stability test and positive bias temperature instability test were also discussed.
High-Performance GaN MOSHEMTs Fabricated With ALD Al2O3 Dielectric and NBE Gate Recess Technology for High Frequency Power Applications
(2017-06-01)
Lin, Yen-Ku
;
Noda, Shuichi
;
Huang, Chia-Ching
;
Lo, Hsiao-Chieh
;
Wu, Chia-Hsun
High-performance GaN metal-oxidesemi-conductor high-electron-mobility transistors (MOSHEMTs) using Al2O3 gate dielectric deposited by atomic layer deposition (ALD) and damage-free neutral beam etch (NBE) gate recess process for millimeter-wave power applications are demonstrated. The high-quality ALD Al2O3 reduces the gate leakage current of the device and the NBE method eliminates the plasma-induced defects in the nitride materials. The MOSHEMT device fabricated exhibits a high maximum drain current density (I-DS,I-max ) of 1.65 A/mm and a high peak extrinsic transconductance (g(m.ext) ) of 653 mS/mm. The MOSHEMT device also demonstrates excellent RF performances, including f(T)/f(MAX) = 183/191 GHz, NFmin = 2.56 dB with G(AS) = 5.61 dB at 54 GHz, and an output power density of 2.7 W/mm associated with a power-added efficiency of 20.9% and a linear power gain of 9.4 dB at 38 GHz. To the best of our knowledge, the noise performance at 54 GHz is the best reported so far for the AlGaN/GaN HEMTs.
High-Performance Normally-OFF GaN MIS-HEMTs Using Hybrid Ferroelectric Charge Trap Gate Stack (FEG-HEMT) for Power Device Applications
(2018-07-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
;
Liu, Shih-Chien
;
Hsieh, Ting-En
;
Lumbantoruan, Franky Juanda
A GaN metal-insulator-semiconductor-high electron mobility transistor (HEMT) using hybrid ferroelectric charge trap gate stack (FEG-HEMT) is demonstrated for normally-OFF operation. The ferroelectric (FE) polarization increases the number of trapped charges in the HfON charge trapping layer, leading to high positive threshold voltage (V-th) shift for the normally-OFF device. Besides, under the positive bias temperature instability (PBTI) test, the internal electric field induced by FE polarization causes smoother slope of the conduction band in FE gate stack, resulting in better V-th stability. With the proposed hybrid FE charge trap gate stack, the device exhibits a high V-th of +2.71 V at I-DS = 1 mu A/mm, a high maximum current density of 820 mA/mm and low on-resistance (R-ON) of 11.1 Omega . mm. The FE device also shows good V-th-temperature stability compared to the non-FE device results. Besides, a high current device with 40 A is also fabricated in this letter to demonstrate the feasibility of the proposed FEG-HEMT device for high power device application.
InGaAs QW-MOSFET Performance Improvement Using a PEALD-AlN Passivation Layer and an In-Situ NH3 Post Remote-Plasma Treatment
(2017-03-01)
Chang, Po-Chun
;
Luc, Quang-Ho
;
Lin, Yueh-Chin
;
Lin, Yen-Ku
;
Wu, Chia-Hsun
In this letter, we report on the impact of a PEALD-AlN interfacial passivation layer (IPL) and an in-situ NH3 post remote-plasma (PRP) treatment onto InGaAs quantum-well MOSFETs with Ti/HfO2/InGaAs gate stack. Transistors with gate lengths down to 80 nm have been fabricated and characterized. Due to the excellent interfacial quality of HfO2/AIN/InGaAs, the subthreshold swing and the peak effective channel mobility have been improved to 93 mV/decade and 4253 cm2/Vs, respectively. The drain current has also shown a 4.6-fold enhancement, to 164mA/mm(I-OFF = 100 nA/mu m DD = 0.5V), compared with the HfO2 control device. The results also show that the HfO2/AIN device exhibits better immunity to short-channel effects (SCEs) than the HfO2 control device. Furthermore, during positive bias temperature instability stress, a smaller V-TH and a lower Gm were observed for the sample with an AIN IPL and NH3 PRP treatment, indicating that it is more reliable than the sample without any IPL or plasma treatment.
AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications (vol 37, pg 1395, 2016)
(2017-01)
Lin, Yen-Ku
;
Noda, Shuichi
;
Lo, Hsiao-Chieh
;
Liu, Shih-Chien
;
Wu, Chia-Hsun
AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications (vol 37, pg 1395, 2016)
(2017-01)
Lin, Yen-Ku
;
Noda, Shuichi
;
Lo, Hsiao-Chieh
;
Liu, Shih-Chien
;
Wu, Chia-Hsun
AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications
(2016-11)
Lin, Yen-Ku
;
Noda, Shuichi
;
Lo, Hsiao-Chieh
;
Liu, Shih-Chien
;
Wu, Chia-Hsun
The electrical performances of gate-recessed AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated using the damage-free neutral beam etching (NBE) method are demonstrated. The NBE method could eliminate the plasma-induced defects generated by irradiating ultraviolet/VUV photons in the conventional inductively coupled plasma reactive ion etching method. The AlGaN/GaN HEMT device fabricated using the new gate recess process exhibited superior electrical performances, including a maximum drain current density (I-DS,I-max) of 1.54 A/mm, low 1/f noise, a current-gain cutoff frequency (f(T)) of 153 GHz, a maximum frequency of oscillation (f(MAX)) of 167 GHz, and a minimum noise figure (NFmin) of 3.28 dB with an associated gain (G(AS)) of 5.06 dB at 54 GHz. Such superior characteristics confirm the inherent advantages of adopting the damage-free NBE process in fabricating GaN devices for millimeter-wave applications.

學術出版;;Publications

Browse

Filters

Settings

Sort By

Results per page

🏛️國立陽明交通大學機構典藏

Search Results