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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作,涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.
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Item type:Item, Improved Charge Pump Design and Ex Vivo Experimental Validation of CMOS 256-Pixel Photovoltaic-Powered Subretinal Prosthetic Chip(2020-05-01) ;Kuo, Po-Han ;Wong, Oi-Ying ;Tzeng, Chi-Kuan ;Wu, Pu-WeiChiao, Chuan-ChinAn improved design of CMOS 256-pixel photovoltaic-powered implantable chip for subretinal prostheses is presented. In the proposed subretinal chip, a high-efficiency fully-integrated 4x charge pump is designed and integrated with on-chip photovoltaic (PV) cells and a 256-pixel array with active pixel sensors (APS) for image light sensing, biphasic constant current stimulators, and electrodes. Thus the PV voltage generated by infrared (IR) light can be boosted to above 1V so that the charge injection is increased. The proposed chip adopts the 32-phase divisional power supply scheme (DPSS) to reduce the required supply current and thus the required area of the PV cells. The proposed chip is designed and fabricated in 180-nm CMOS image sensor (CIS) technology and post-processed with biocompatible IrOx electrodes and silicone packaging. From the electrical measurement results, the measured stimulation frequency is 28.3 Hz under the equivalent electrode impedance load. The measured maximum output stimulation current is 7.1 mu A and the amount of injected charges per pixel is 7.36 nC under image light intensity of 3200 lux and IR light intensity of 100 mW/cm(2). The function of the proposed chip has been further validated successfully with the ex vivo experimental results by recording the electrophysiological responses of retinal ganglion cells (RGCs) of retinas from retinal degeneration (rd1) mice with a multi-electrode array (MEA). The measured average threshold injected charge is about 3.97 nC which is consistent with that obtained from the patch clamp recording on retinas from wild type (C57BL/6) mice with a single electrode pair.Item type:Item, An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS(2019-05-01) ;Liu, Chi-Wei ;Chen, Yi-Lun ;Liao, Pei-Chun ;Lin, Shiau-PinWang, Ting-WeiThis brief presents a high-efficiency battery management unit combining a single-inductor dual-output (SIDO) buck converter with two charge pumps (CPs) to provide three voltage levels (6 V, -6 V, and 2 V) for neuron stimulators in implantable medical devices. The stacked power stage in the buck converter mitigates the voltage stress issue in the power stage to manage 3.2-4.8 V battery voltage. By cascading a buck converter and CPs, the voltage across the CP power stage is reduced to generate 6 V and -6 V high voltage outputs without using high voltage devices. As a result, the proposed battery management could provide 6 V, -6 V, and 2 V output voltages from 3.2 to 4.8 V input voltage using a 180-nm standard CMOS process. The measurement results demonstrate that the proposed battery management achieved a peak efficiency of 82.9% with an available input voltage of 3.2-4.8 V.Item type:Item, A Fully-Integrated Charge Pump for Self-Powered Implantable Retinal Prostheses(2016) ;Wong, Oi-Ying ;Chen, Po-Hung ;Wu, Chung-Yu ;電子工程學系及電子研究所生醫電子轉譯研究中心This paper presents a compact fully-integrated charge pump based voltage doubler for self-powered implantable retinal prostheses. The target input voltage is 0.55 V to meet the output voltage of on-chip photovoltaic cells, and the target output is around 1 V to provide sufficient current for neuron stimulation. Several techniques are adopted in the proposed design, including gate-boosting circuits to enhance current driving capability, a time-interleaving technique to reduce the size of the output capacitor, and a non-overlapping clock generator to suppress the shoot-through current. The proposed charge pump was implemented in 0.18 mu m CMOS process with core chip area of 700 mu m x 280 mu m. The measurement results demonstrate that the proposed charge pump is capable of providing around 1 V output from an input voltage of 0.55 V with 500 mu A loading current. The peak power efficiency is 73.4 % and the total area is 700 mu m x 280 mu m.