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Now showing 1 - 10 of 33

0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process
(2018-01-01)
Chan, Yun-Sheng
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Huang, Po-Tsang
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Wu, Shang-Lin
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Lung, Sheng-Chi
;
Wang, Wei-Chang
This paper presents a near-threshold configurable ternary content addressable memory (TCAM) design for energy-constrained neural network or software-defined network (SDN) applications. A TCAM architecture based on foundry-based 6T SRAM mini-array improves area efficiency and minimizes disturbs to enable operation down to 0.4V, and provides configurable lookup tables for users. To minimize dynamic power consumption, hierarchical precharge structure (HPRE) and don't-care based ripple search-line scheme are utilized for decreasing both the switching activities and wire capacitance. Moreover, power-gating technique, self-timed control and V-trip-tracking write-assist are used to reduce standby power, speed-up propagation delays of global signals and improve write-ability at low voltage, respectively. A reconfigurable TCAM is implemented using UMC 28nm high-k metal gate (HKMG) CMOS process. The design achieves operating frequency of 240MHz (20MHz) with energy consumption of 1.146 (0.621) fJ/bit/search at 0.9V (0.4V).
28nm Near/Sub-Threshold Dual-Port FIFO Memory for Shared Queues in Multi-Sensor Applications
(2018-01-01)
Wu, Yi-Chun
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Huang, Po-Tsang
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Wu, Shang-Lin
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Lung, Sheng-Chi
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Wang, Wei-Chang
For an energy-limited multi-sensing platform, ultra-low-power queueing design is one of the critical challenge to store low-speed sensing data with various sampling frequencies. In this paper, a near/sub-threshold dual-port first-in-first-out (FIFO) memory is proposed for shared queues in a unified queuing architecture. This ultra-lowpower FIFO memory is designed and implemented using bitinterleaved 12T near-/sub-threshold dual-port SRAM bit-cells, write/read-assist circuitries, and adaptive timing tracking circuits. The 12T bit-cell eliminates both read and write half-select disturbance. Additionally, an adaptive timing tracing circuitry and negative bit-line circuits are employed to against PVT variation and to enhance write ability, respectively. Furthermore, the self-timed pointers and short ripple bit-lines are designed to avoid global long metal lines with large loading. A 256x16 dual-port FIFO memory is implemented in UMC 28nm HKMG CMOS technology. This FIFO memory can be operated at 0.4V with 10MHz for read operations. Moreover, up to 60% power reduction can be achieved based on the proposed design techniques.
A global optimized neuro-fuzzy system using artificial bee colony evolutionary algorithm
(2015-01-01)
Liu, Yu-Ting
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Lin, Yang-Yin
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Hsieh, Tsung-Yu
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Wu, Shang-Lin
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Lin, Chin-Teng
This paper proposes a novel Takagi-Sugeno-Kang-type (TSK-type) neuro-fuzzy system (NFS), which utilizes the artificial bee colony (ABC) evolutionary algorithm for parameter optimization. The ABC evolutionary algorithm was developed based on imitating foraging behavior of natural bees for numerical optimization problems, and it has been proved to outperform other metaheuristic approaches on different constrain optimization problems in previous studies. The proposed NFS in this paper adopts an adaptive clustering method to generate fuzzy rules for determining the system architecture, and the TSK-type reasoning is employed for the consequent part of each rule. Subsequently, all free parameters in the NFS designed, including the premise and the consequent parameters, will be optimized by ABC algorithm. This study compares the performance of ABC algorithm with that of Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Differential Evolution (DE). The simulation results show that the performance of ABC algorithm is superior to that of the mentioned algorithms for solving dynamic system problems.
A 64-CHANNEL WIRELESS NEURAL SENSING MICROSYSTEM WITH TSV-EMBEDDED MICRO-PROBE ARRAY FOR NEURAL SIGNAL ACQUISITION
(2017-01-01)
Huang, Yu-Chieh
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Huang, Po-Tsang
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Hu, Yu-Chen
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Wu, Shang-Lin
;
You, Yan-Huei
To enhance the signal integrity of high-density neural-sensing signals, this work presents an implantable high spatial resolution mu-probe array with through-silicon via (TSV) 2.5D integration technology that realizes a miniaturized implantable device on flexible printed circuit (FPC) interposer. The proposed microsystem was composed of two 32-channel neural sensing chips and one radio frequency chip for neural signal processing. The mu-probe array can achieve better signal-to-noise ratio with neural-signal acquisition and processing circuit composed of a pseudo-resistor-based analog front-end amplifier. Moreover, a receiving antenna is also implemented on the backside of FPC for wireless data and power transmission. The feasibility of the proposed mu-probe array, Tx and Rx antenna, 32-channel neural sensing circuits in the 64-channel wireless microsystem have been successfully demonstrated for future integration and animal experiments.
An Implantable 128-Channel Wireless Neural-Sensing Microsystem using TSV-Embedded Dissolvable mu-Needle Array and Flexible Interposer
(2017-01-01)
Huang, Po-Tsang
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Huang, Yu-Chieh
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Wu, Shang-Lin
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Hu, Yu-Chen
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Lu, Ming-Wei
For implanted neural-sensing devices, one of the remaining challenges is to transmit stable power/data (P/D) transmission for high spatiotemporal resolution neural data. This paper presents a miniaturized implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable mu-needle array, a flexible interposer and 4 dies by 2.5D/3D TSV heterogeneous SiP technology. The 4 dies are 2 neural-signal acquisition ICs implemented by 90nm CMOS, 1 neural-signal processor by 40nm CMOS and 1 wireless P/D transmission circuitry by 0.18 mu m CMOS. Thus, the proposed wireless microsystem realizes 128-channel neural-signal sensing within the area of 5mm x 5mm, neural feature extraction and wireless P/D transmission using an on-interposer inductor. The overall average power of the circuits in this microsystem is only 9.85mW.
Area-Power-Efficient 11-Bit Hybrid Dual-Vdd ADC with Self-Calibration for Neural Sensing Application
(2016-01-01)
Chen, Jr-Ming
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Huang, Po-Tsang
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Wu, Shang-Lin
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Hwang, Wei
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Chuang, Ching-Te
'Miniaturized neural sensing microsystem has become increasingly important for brain function investigation. This paper presented a low voltage area-power-efficient 11-bit hybrid analog-to-digital convertor (ADC) with self-calibration for neural sensing application. To reduce the total amount of capacitance, the proposed hybrid ADC is composed of 3 bit coarse-tune and 8 bit fine-tune with delay-lined based ADC and successive approximation register (SAR) ADC. The three most significant bits are detected by a modified vernier structure delay-line-based ADC. Self-timed power management including dual voltage supply, power-gating and multi-threshold CMOS are employed and the capacitance mismatch due to process variation is compensated using a self-calibration scheme. The proposed 11 bit ADC is implemented in TSMC 90nm general propose (GP) CMOS technology. Post-sim results indicate that ENOB of 9.71-bits at 32KS/s sampling rate can be achieved with only 982nW power consumption and 0.026-mm(2). The FOM of the proposed hybrid ADC is 36.75fJ/conversion-step.
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
(2017-07-01)
Wu, Shang-Lin
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Li, Kuang-Yu
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Huang, Po-Tsang
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Hwang, Wei
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Tu, Ming-Hsien
This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high-kappa metal-gate (H kappa MG) CMOS technology with macro area of 1058.22 x 374.76 mu m(2). Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN) without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25(omicron).
An Advanced 2.5-D Heterogeneous Integration Packaging for High-Density Neural Sensing Microsystem
(2017-04-01)
Hu, Yu-Chen
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Huang, Yu-Chieh
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Huang, Po-Tsang
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Wu, Shang-Lin
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Chang, Hsiao-Chun
In the traditional neural sensing microstructure, the limited metal line pitch and the metal layer numbers restrict the neural signal routing ability from electrodes to circuit chips. Miniature packaging and excessive noise interference bottlenecks are some of the challenges faced by the electrodes and circuit chips integration with traditional wire bonding. This paper proposes a 2.5-D heterogeneous integration neural sensing microsystem based on the silicon substrate to overcome these issues. With standard semiconductor and 3-D integration processes, high-channel-density (256 channels at 25 mm(2)) neural sensing microsystem is achieved. Through silicon via provides the shortest vertical interconnection and dramatically minimizes the packaging. Furthermore, the interposer can carry multiple chips to enhance the function of the biosensor. Electrical characteristics and reliability examinations reveal its high quality and great performance as compared to traditional approaches. This novel highly integrated neural sensing microsystem is expected to contribute to the biomedical field for exploring and solving unknown biological mysteries.
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes
(2017-10-01)
Huang, Yu-Chieh
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Huang, Po-Tsang
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Wu, Shang-Lin
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Hu, Yu-Chen
;
You, Yan-Huei
Highly integrated neural sensing microsystems are crucial to capture accurate signals for brain function investigations. In this paper, a 256-channel neural sensing microsystem with a sensing area of 5 x 5 mm(2) is presented based on 2.5-D through-silicon-via (TSV) integration. This microsystem composes of dissolvable mu-needles, TSV-embedded mu-probes, 256-channel neural amplifiers, 11-bit area-power-efficient successive approximation register analog-to-digital converters, and serializers. This microsystem can detect 256 electrocorticography and local field potential signals within a small area of 5 mm x 5 mm. The neural amplifier realizes 57.8 dB gain with only 9.8 mu W per channel. The overall power of this microsystem is only 3.79mW for 256-channel neural sensing. A smaller microsystem with dimension of 6 mm x 4 mm has been also implanted into rat brain for somatosensory evoked potentials (SSEPs) recording by using contralateral and ipsilateral electrical stimuli with intensity from 0.2 to 1.0 mA, and successfully observed different SSEPs from left somatosensory cortex of a rat.
Fuzzy Integral With Particle Swarm Optimization for a Motor-Imagery-Based Brain-Computer Interface
(2017-02)
Wu, Shang-Lin
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Liu, Yu-Ting
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Hsieh, Tsung-Yu
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Lin, Yang-Yin
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Chen, Chih-Yu
A brain-computer interface (BCI) system using electroencephalography signals provides a convenient means of communication between the human brain and a computer. Motor imagery (MI), in which motor actions are mentally rehearsed without engaging in actual physical execution, has been widely used as a major BCI approach. One robust algorithm that can successfully cope with the individual differences in MI-related rhythmic patterns is to create diverse ensemble classifiers using the subband common spatial pattern (SBCSP) method. To aggregate outputs of ensemble members, this study uses fuzzy integral with particle swarm optimization (PSO), which can regulate subject-specific parameters for the assignment of optimal confidence levels for classifiers. The proposed system combining SBCSP, fuzzy integral, and PSO exhibits robust performance for offline single-trial classification of MI and real-time control of a robotic arm using MI. This paper represents the first attempt to utilize fuzzy fusion technique to attack the individual differences problem of MI applications in real-world noisy environments. The results of this study demonstrate the practical feasibility of implementing the proposed method for real-world applications.

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