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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Yu, Shao-MingHas files: No

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Now showing 1 - 10 of 14
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    A compact model for electrostatic discharge protection nanoelectronics simulation
    (2005)
    Chou, Hung-Mu
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    Yu, Shao-Ming
    ;
    Lee, Jam-Wem
    ;
    Li, Yiming
    ;
    電信工程研究所
    In nanoelectronics, snapback phenomena play an important role in electrostatic discharge (ESD) protection devices, in particular for gigascale, very large scale integration (VLSI) circuit design. In this paper we present a new ESD equivalent circuit model for deep submicrion and nanoscale semiconductor device simulation. By considering the geometry effect in the formulation of snapback characteristics, our model can be directly incorporated into electronic circuit simulation for the whole chip ESD protection circuit design. With the developed ESD model, we can investigate robust enhancement problems and perform a SPICE based whole chip ESD protection circuit design in nanoelectronics.
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    A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation
    (2006-07-01)
    Li, Yiming
    ;
    Yu, Shao-Ming
    ;
    資訊工程學系
    ;
    電信工程研究所
    ;
    Department of Computer Science
    In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrodinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.
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    Monotone iterative method for numerical solution of nonlinear ODEs in MOSFET RF circuit simulation
    (2005)
    Li, Yiming
    ;
    Yu, Shao-Ming
    ;
    Wang, Chuan-Sheng
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    (MOSFET) radio frequency (RF) circuit as a system of nonlinear ordinary differential equations. Then we solve them with the waveform relaxation method, the monotone iterative method, and Runge-Kutta method directly in time domain. With the monotone iterative method, we prove each decoupled and transformed circuit equation converges monotonically. In comparison with the HSPICE outputs, results calculated with our method are stable and robust in both the time and frequency domains. Convergence properties for the monotone iterative and outer iterative loops axe also presented and discussed. This method provides an alternative in the time domain numerical solution of MOSFET RF circuit equations.
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    Parallel simulation of deep sub-micron double-gate metal-oxide-semiconductor field effect transistors
    (2005)
    Yu, Shao-Ming
    ;
    Chou, Hung-Mu
    ;
    Lo, Shih-Ching
    ;
    資訊工程學系
    ;
    Department of Computer Science
    Drift-Diffusion Density Gradient model (DD-DG) is the most popular model for simulating carrier transport phenomena in sub-micron semiconductor device, especially in two- or three-dimensional space. In deep sub-micron regime, the width effects cannot be neglected while simulating, i.e., three-dimensional simulation must be considered. However, three-dimensional computing is time-consuming. Fortunately, the dilemma of time consuming or rough approximation can be overcame by advanced computing technique. In this paper, we employ a parallel direct solving method to simulate double-gate metal-oxide-semiconductor field effect transistors (DG-MOSFET). The computational benchmarks of the parallel simulation, parallel speedup, load balance, and efficiency are studied in this work. Parallel numerical simulation of semiconductor devices is shown to be an indispensable tool for fast characterization and optimal design of semiconductor devices.
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    Parallel numerical solution to large-scale eigenvalue problem in master equation of protein folding kinetics
    (2006)
    Li, Yiming
    ;
    Yu, Shao-Ming
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    A master equation characterizes the time-evolution of trajectories, the transition of states in protein folding kinetics. Numerical solution of the master equation requires calculating eigenvalues for the corresponding large scale eigenvalue problem. In this paper, we present a parallel computing technique to compute the eigenvalues of the matrix with an N-dimensional vector of the instantaneous probability of the N conformations. Parallelization of the implicitly restarted Arnoldi method is successfully implemented on a PC-based Linux cluster. The parallelization scheme used in this work mainly partitions the operations of the matrix. For the Arnoldi factorization, we replicate the upper Hessenberg matrix H-m for each processor and distribute the set of Arnoldi vectors V-m among processors. Each processor performs its own operations. This algorithm is implemented on a PC-based Linux cluster with message passing interface (MPI) libraries. Our preliminary numerical experiment performing on the 32-nodes PC-based Linux cluster has shown that the maximum difference among CPUs is within 10%. A 23 times speedup and 72% parallel efficiency are also attained for the tested cases. This approach enables us to explore large scale dynamics of protein-folding.
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    A unified optimization framework for real world problems
    (2006)
    Li, Yiming
    ;
    Yu, Shao-Ming
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    In this paper, an object-oriented unified optimization framework (UOF) for general problem optimization is developed. Based on global evolutionary algorithms, numerical deterministic methods, and C++ objective design, the UOF itself has great potential to perform optimization operations on kind of problems. The UOF provides basic interfaces to define a general problem and generic solver;, hence the two different parts are bridged. The UOF components are categorized into problem and solver parts and work independently. Therefore, reutilization of the high level code allows an adaptation to new problem and solver quickly. We customize the UOF to deal with some real world optimization problems.
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    A quantum hydrodynamic simulation of strained nanoscale VLSI device
    (2006)
    Lo, Shih-Ching
    ;
    Yu, Shao-Ming
    ;
    資訊工程學系
    ;
    Department of Computer Science
    Strained silicon field effect transistor (FET) has been known for enhancing carrier mobility. The stained Si channel thickness, the Si1-xGex composition fraction and the Si1-xGex layer thickness are three crucial parameters for designing strained Si/SiGe MOSFET. Mobility enhancement and device reliability may be unnecessarily conservative. In this paper, numerical investigation of drain current, gate leakage and threshold voltage for strained Si/SiGe MOSFET are simulated under different device profiles. According to our results, the optimal combination of parameters are as follows: stained Si channel thickness is 7 nm, Ge content is 20%, and the Si1-xGex layer thickness should be chosen between 20 similar to 50 nm.
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    Discrete Dopant Induced Electrical and Thermal Fluctuation in Nanoscale SOI FinFET
    (2007)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    Yu, Shao-Ming
    ;
    Huang, Hsuan-Ming
    ;
    電信工程研究所
    The International Roadmap for Semiconductors has forecasted a transition from conventional bulk device to silicon-on-insulator (SOI) one, and then to multiple-gate SOI for high-performance devices. Impact of the discrete-dopant number and discrete-dopant position on device characteristics is crucial for nanoscale semiconductor devices. In this paper, the discrete dopant induced electrical and thermal fluctuation of 16nm SOI FinFETs is for the first time explored. A three-dimensional atomistic" device simulation with quantum hydrodynamic equation is proposed and performed for electrical and thermal characteristics of the discrete dopant fluctuated SOI FinFETs. Discrete dopants are statistically positioned in the 3D channel region to study associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Effect of the discrete-dopant-number- and discrete-dopant-position-induced fluctuations on device characteristic including variations of the lattice and electron temperatures are advanced. The large-scale computational statistics study provides us an insight into the fluctuation of electrical and thermal characteristics and mechanism of immunity against fluctuation in SOI FinFETs.
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    A comparative study of foreign direct investment flow using diffusion models
    (2007)
    Li, Yiming
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    Chiang, Yi-Hui
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    Yu, Shao-Ming
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    Chiang, Su-Yun
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    Hung, C. -H.
    In this work, we apply an improvement dynamic model of the foreign direct investment (FDI) flow to analyze the evolution of FDI flow. In comparison with the fundamental growth model of FDI, the simulation result is further accurate if the asymmetric growth pattern and heterogeneity of the potential adopters are considered. According to the result, the internal influence dominates the growth of FDI flow from Taiwan to China during 2001-2006, taking the electronics industry for example.
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    A simulation-based hybrid optimization technique for low noise amplifier design automation
    (2007)
    Li, Yiming
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    Yu, Shao-Ming
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    Li, Yih-Lang
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    電信工程研究所
    ;
    Institute of Communications Engineering
    In this paper, a simulation-based optimization technique for integrated circuit (IC) design automation is presented. Based on a genetic algorithm (GA), Levenberg-Marquardt (LM) method, and circuit simulator, a window-interfaced prototype of computer-aided design (CAD) is developed for IC design. Considering low noise amplifier (LNA) IC, we simultaneously evaluate specifications including S parameters, K factor, noise figure, and input third-order intercept point in the optimization process. If the simulated results meet the aforementioned constraints, the prototype outputs the optimized parameters. Otherwise, CAD activates GA for global optimization; simultaneously, LM method searches solutions with the results of GA. The prototype then calls a circuit simulator to compute and evaluate newer results until all specifications are matched. More than fifteen parameters including device sizes, passive components, and biasing conditions are optimized for the aforementioned constraints. For LNA IC with 0.18 mu m metal-oxide-silicon filed effect transistors, benchmark results confirm the functionality of the implemented prototype.