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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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    Short-channel poly-Si thin-film transistors with ultrathin channel and self-aligned tungsten-clad source/drain
    (2004)
    Zan, HW
    ;
    Chang, TC
    ;
    Shih, PS
    ;
    Peng, DZ
    ;
    Kuo, PY
    A short-channel polycrystalline silicon (poly-Si) thin-film transistor (W/L=10 mum/3 mum) with an ultrathin channel (30 nm) and self-aligned tungsten-clad source/drain structure is demonstrated. With WF6 and SiH4 gas flow ratio of 40/12, selectively deposited tungsten film over 100 nm thick can be easily grown on source/drain regions. As a result, the parasitic source/drain resistance is greatly reduced, leading to improvement of device driving ability. Because tungsten deposition can be carried out at a low processing temperature of 300degreesC, the proposed simple structure is compatible with conventional top-gate structure and can be readily applied to low-temperature poly-Si fabrication. (C) 2003 The Electrochemical Society.
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    Enhanced performance of poly-Si thin film transistors using fluorine ions implantation
    (2005)
    Tu, CH
    ;
    Chang, TC
    ;
    Liu, PT
    ;
    Zan, HW
    ;
    Tai, YH
    Fluorine (F)-implanted polycrystalline silicon thin-film transistor (poly-Si TFT) are proposed for the enhancement of device performance. A significant improvement in electrical characteristics, such as I-ON/I-OFF ratio, and field effect mobility, can be realized in the new thin-film transistor. The field effect mobility for F-implanted poly-Si TFTs is 53.82 cm(2)/V-s, and higher than 19.74 cm(2)/V-s in conventional SPC poly-Si TFTs. Furthermore, the F-implanted poly- Si TFT exhibits high immunity against hot carrier effect and improved electrical reliability. The manufacturing processes are simple and without additional thermal annealing steps, thereby compatible with the conventional TFT fabrication processes. (c) 2005 The Electrochemical Society. All rights reserved.
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    Improvement of reliability for polycrystalline thin-film transistors using self-aligned fluorinated silica glass spacers
    (2005)
    Tu, CH
    ;
    Chang, TC
    ;
    Liu, PT
    ;
    Zan, HW
    ;
    Tai, YH
    Polycrystalline silicon thin-film transistors (poly-Si TFTs) with self-aligned fluorine-doped SiO2 (FSG) spacer were investigated in this study. The presence of FSG spacers can effectively reduce the lateral electrical field near the drain side of a poly-Si TFT device, and strongly passivate Si dangling bonds at the grain boundaries. The significant enhancement in electrical performance suppresses serious kink effect and improves electrical reliability of poly-Si TFTs effectively. In addition, the proposed poly-TFT structure is uncomplicated and compatible with existing TFT manufacturing processes. (c) 2005 The Electrochemical Society.
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    Anomalous substrate current in polycrystalline silicon thin-film transistors
    (2003)
    Zan, HW
    ;
    Chen, SC
    ;
    Wang, SH
    ;
    Chang, CY
    ;
    電子工程學系及電子研究所
    In this paper, the substrate current of polycrystalline silicon thin-film transistors was measured and investigated the first time. With typical T-gate pattered structure, an abnormal high substrate current was found while devices were operated under high gate voltage. This is generated from the parasitic tunnelling current between the n+ inversion region and the p+ body region. Under lower gate voltage, substrate current generated from impact ionization effect is also observed and characterized. After extracting fitting parameters from the device characteristics, a simple physically-based model was established and compared with the measured results. A plausible grain boundary scattering effect was included in the proposed model. Good agreements were found through a wide range of gate bias and various drain bias, verifying the validity of this unified model.
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    High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channels
    (2004)
    Wu, YC
    ;
    Chang, CY
    ;
    Chang, TC
    ;
    Liu, PT
    ;
    Chen, CS
    We have investigated the lightly-doped drain (LDD) polysilicon thin-film transistors (poly-Si TFTs) with a series of multi-channel with different widths. The ten 67 nm-wide split channels TFT has best gate control due to its tri-gate structure, and has lowest poly-Si grain boundary defects, which were passivated by NH3 plasma effectively due to its split nano-wires structure. The proposed TFT exhibits high performance electrical characteristics, such as a high ON/OFF current ratio (>10(9)), a steep subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL), suppressed kink-effect, and superior reliability.