學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Search Results

Now showing 1 - 10 of 25

適用於GHz頻段之輸出入靜電放電防護技術與銲墊設計
(2001)
柯明道
;
KER MING-DOU
;
交通大學電子工程研究所
Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses
(2008-09-01)
Chen, Shih-Hung
;
Ker, Ming-Dou
;
Hung, Hsiang-Pin
;
電機學院
;
College of Electrical and Computer Engineering
Several complex electrostatic discharge (ESD) failure mechanisms have been found in the interface circuits of an IC product with multiple separated power domains. In this case, the machine-model (MM) ESD robustness cannot achieve 150 V in this IC product with separated power domains, although it can pass the 2-kV human-body-model (HBM) ESD test. The negative-to-VDD (ND) mode MM ESD currents were discharged by circuitous current paths through interface circuits to cause the gate oxide damage, the junction filament, and the contact destruction of the internal transistors. The detailed discharging paths of ND-mode ESD failures were analyzed in this paper. In addition, some ESD protection designs have been illustrated and reviewed to further comprehend the protection strategies for cross-power-domain ESD events. Moreover, one new active ESD protection design for the interface circuits between separated power domains has been proposed and successfully verified in a 0.13-mu m CMOS technology. The HBM and MM ESD robustness of the separated-power-domain interface circuits with the proposed active ESD protection design can achieve over 4 kV and 400 V, respectively.
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs
(2011-02-01)
Ker, Ming-Dou
;
Chen, Wen-Yi
;
Shieh, Wuu-Trong
;
Wei, I-Ju
;
電機學院
For integrated circuits (ICs) with voltage programming pin (V(PP) pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the V(PP) pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to V(DD) cannot be applied to such V(PP) pin. In this work, a new ESD protection design is proposed to improve ESD robustness of V(PP) pin with the consideration of the mistriggering issue when V(PP) programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.
Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications
(2014-06-01)
Chen, Shih-Hung
;
Linten, Dimitri
;
Scholz, Mirko
;
Huang, Yu-Ching
;
Hellings, Geert
CDM ESD events can be a potential threat to SoC designs or heterogeneous 3D ICs with multiple power domains. Inter-layer ( or interface) circuits may need a local CDM ESD clamp that can prevent the unexpected failure under CDM ESD stress. In this letter, two local CDM ESD clamp circuits are proposed. They show better clamping efficiency under 2-ns vfTLP stress.
On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection
(2014-10-01)
Chuang, Che-Hao
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel on-chip transient voltage suppressor (TVS) integrated with the silicon-based transceiver IC has been proposed and verified in a 0.8 mu m bipolar CMOS DMOS (BCD) process for IEC 61000-4-2 system-level electrostatic discharge (ESD) protection. The structure of on-chip TVS is a high-voltage dual silicon-controlled rectifier (DSCR) with +/- 16 V of high holding voltage (Vh) under the evaluation of the transmission line pulsing (TLP) system with the pulse width of 100 ns. With the high holding current (Ih) of on-chip TVS, this design can pass +/- 200 mA latch-up testing. Therefore, the on-chip TVS can be safely applied to protect the RS232 transceiver with the signal level of +/- 15 V. The RS232 transceiver IC with on-chip TVS has been evaluated to pass the IEC61000-4-2 contact +/- 12 kV stress without any hardware damages and latch-up issue. Moreover, the proposed RS232 transceiver IC has been verified to well protect the system over the IEC 61000-4-2 contact +/- 20 kV stress (class B) in the notebook applications.
On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
(2014-03-01)
Ker, Ming-Dou
;
Yeh, Chih-Ting
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
CMOS technology has been widely used to produce many integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously increases the difficulty of electrostatic discharge (ESD) protection design. The power-rail ESD clamp circuit has been the key circuit to perform the whole-chip ESD protection scheme. Some ESD detection circuits were developed to trigger on ESD devices across the power rails to quickly discharge ESD current away from the internal circuits. Therefore, on-chip ESD protection circuits must be designed with the consideration of standby leakage to minimize the power consumption and the possibility of malfunction to normal circuit operation. The design of power-rail ESD clamp circuits with low standby leakage current and high efficiency of layout area in nanoscale CMOS technology is reviewed in this paper. The comparisons among those power-rail ESD clamp circuits are also discussed.
Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies
(2011-06-01)
Ker, Ming-Dou
;
Lin, Chun-Yu
;
Hsiao, Yuan-Wen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
CMOS technology has been widely used to implement radio-frequency integrated circuits (RF ICs). However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of RF ICs. Therefore, on-chip ESD protection designs must be added at all input/output pads in RF circuits against ESD damages. To minimize the impacts from ESD protection circuit on RF performances, ESD protection circuit at input/output pads must be carefully designed. An overview on ESD protection designs with low parasitic capacitance for RF circuits in CMOS technology is presented in this paper. The comparisons among these ESD protection designs are also discussed. With the reduced parasitic capacitance, ESD protection circuit can be easily combined or co-designed with RF circuits. As the operating frequencies of RF circuits increase, on-chip ESD protection designs for RF applications will continuously be an important design task.
Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process
(2013-10-01)
Altolaguirre, Federico Agustin
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new silicon controlled rectifier-based power-rail electrostatic discharge (ESD) clamp circuit was proposed with a novel trigger circuit that has very low leakage current in a small layout area for implementation. This circuit was successfully verified in a 40-nm CMOS process by using only low-voltage devices. The novel trigger circuit uses a diode-string based level-sensing ESD detection circuit, but not using MOS capacitor, which has very large leakage current. Moreover, the leakage current on the ESD detection circuit is further reduced, adding a diode in series with the trigger transistor. By combining these two techniques, the total silicon area of the power-rail ESD clamp circuit can be reduced three times, whereas the leakage current is three orders of magnitude smaller than that of the traditional design.
Semiself-Protection Scheme for Gigahertz High-Frequency Output ESD Protection
(2011-07-01)
Lee, Jian-Hsing
;
Huang, Shao-Chang
;
Su, Hung-Der
;
Chen, Ke-Horng
;
電控工程研究所
In this paper, a semiself-protection scheme is proposed and developed for gigahertz output electrostatic-discharge (ESD) protection. The output transistor acts as a trigger device to trigger the ESD protection device, and then, it is turned off when the ESD protection device turns on. Thus, the capacitance of a gigahertz high-frequency output pad can be minimized because this scheme is without any additional trigger device or any passive component.
Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
(2013-02-01)
Lin, Chun-Yu
;
Tsai, Shiang-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
The signal swing at output pad of some radio-frequency (RF) power amplifiers (PAs) may be higher than the supply voltage. To protect the gigahertz large-swing power amplifier from electrostatic discharge (ESD) damage in nanoscale CMOS process, a large-swing-tolerant ESD protection circuit is presented in this paper. The proposed ESD protection circuit had been designed, fabricated, and characterized in a 65-nm CMOS process, where it can achieve low parasitic capacitance, large swing tolerance, high ESD robustness, and good latchup immunity. The proposed ESD protection circuit had been further applied to a 2.4-GHz PA to provide 3-kV human-body-model (HBM) ESD robustness without degrading the RF performances.

學術出版;;Publications

Browse

Filters

Settings

Sort By

Results per page

🏛️國立陽明交通大學機構典藏

Search Results