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Perovskite Oxides as Resistive Switching Memories: A Review
(2014-10-26)
Panda, Debashis
;
Tseng, Tseung-Yuen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Numerous metal-insulator-metal systems demonstrate electrically induced resistive switching effects and have therefore been proposed as the basis for future nonvolatile memories. They combine the advantages of flash memories and dynamic random access memories while avoiding their drawbacks, such as operation speed, power consumption and device integration and scalable issues. The RRAM devices primarily operate at different resistance values to store the digital data and can keep the resistance state without any power supply. Recent advances in the understanding of the resistive switching mechanism are explained by a thermal or electrochemical redox reaction near the interface between the oxide and the top active metal electrode. Here we review the ongoing research and development activities on the perovskite based resistive switching memory devices. The possible switching mechanisms for the resistive switching are described. The effects of crystal structure, dopants, doping concentrations, annealing temperature, device structures and thickness of the active oxide layer on the resistive switching characteristics and consequently the memory performances are also discussed. From this insight, we take a brief look into different effect on the switching of the perovskite material systems.
新穎非揮發性奈米點記憶體在薄膜電晶體上的製作與研究
(2009)
張俊彥
;
CHANG CHUN-YEN
;
國立交通大學電子工程學系及電子研究所
近年來，薄膜電晶體(TFT)與奈米點(nanocrystal)的應用技術發展受到相當大的矚目，薄膜電晶體目前廣為液晶顯示器(LCD)產業所大量使用，而奈米點則是可以運用於在非揮發性儲存記憶體上，因其可以解決傳統上利用複晶矽浮停閘(floating gate)做為載子儲存單元的非揮發性記憶體(例如，快閃記憶體)之元件微縮問題，而本計畫將兩者結合起來，並開發新穎結構的非揮發性奈米點記憶體在薄膜電晶體上，其功能可以運用在堆疊式(stacked)的積體電路晶片、軟性電子與省電的攜帶式產品上，對於SOC(System on Chip)的開發與研究提供一個新的元件結構。複晶矽薄膜電晶體可以在低溫下成長，對於後段製程的熱預算(thermal budget)可以有效的降低，而與奈米點結合，則可以成為新結構的記憶體元件，本計畫即利用先前的薄膜電晶體與奈米點的製作成果技術相互結合來研究此元件的特性，第一年著重於大尺寸的新穎非揮發性奈米點記憶體在薄膜電晶體上的製作與基本電性驗證，利用先前的薄膜電晶體技術與各種不同的奈米點結合(Si、Ge、NiSi、W)，並探討半導體與金屬這些不同材料特性會對非揮發性記憶體有何影響，第二年則進而會改變元件結構，利用多重通道與多重閘極，來研究新穎奈米點記憶體的寫入與抹除效應是否會提升其元件速度，且當元件通道結構微縮至奈米尺度時，邊角效應(corner effect)與奈米點的量子效應則會如何主導我們的薄膜電晶體的開關特性，是本計畫要釐清的重點之一。第三年則是著重於已製備完成的元件記憶體特性量測，本實驗團隊將進行記憶體的可靠度分析，不僅進行DC與AC的加壓量測複晶矽薄膜電晶體元件，並改變環境溫度探討儲存載子的活化能影響及儲存效率，對於容忍度(endurance)與保存能力(retention)也將深入測試，藉此製作一個高效能的非揮發性奈米點結合薄膜電晶體的記憶體元件，以確保有機會可以運用在SOC開發上與其他省電的產品上。
Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals
(2010-08-01)
Chiang, Tsung-Yu
;
Wu, Yi-Hong
;
Ma, William Cheng-Yu
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V(g) = 6 V, V(d) = 7 V and V(g) = -7 V, V(d) = 10 V, respectively), greater tolerable gate and drain disturbance (V(t) shift < 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 mu s with a 2-V shift of V(t) under V(g) = V(d) = 6 V operation), good retention time (> 10(8) s for 13% charge loss), and excellent endurance performance (after 10(4) P/E cycles with a memory window of 3 V).
Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation
(2010-12-01)
Chen, Te-Chih
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Chang, Ting-Chang
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Chen, Shih-Ching
;
Hsieh, Tien-Yu
;
Jian, Fu-Yen
This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon structure under OFF-state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant ON-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I-V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point.
Simultaneous quality improvement of tunneling- and interpoly-oxides of nonvolatile memory devices by NH3 and N2O nitridation
(2003-11-01)
Chao, TS
;
Chang, TH
;
電子物理學系
;
Department of Electrophysics
This brief presents a new nitridation process on floating poly-Si gate to improve the quality of both tunneling oxide and interpoly-oxide of nonvolatile memories. Three types of poly-Si for a floating gate have been investigated. We found in-situ doped poly-Si shows the best performance in terms of breakdown field, charge-to-breakdown (Q(BD)) and trapping rate. The Q(BD) of interpoly-oxide can be reached as high as 35 C/cm(2). This scheme is very promising for nonvolatile memory devices.
Dynamic Observation of Phase Transformation Behaviors in Indium(III) Selenide Nanowire Based Phase Change Memory
(2014-09-01)
Huang, Yu-Ling
;
Huang, Chun-Wei
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Chen, Jui-Yuan
;
Ting, Yi-Hsin
;
Lu, Kuo-Chang
Phase change random access memory (PCRAM) has been extensively investigated for its potential applications in next-generation nonvolatile memory. In this study, indium(III) selenide (In2Se3) was selected due to its high resistivity ratio and lower programming current. Au/In2Se3-nanowire/Au phase change memory devices were fabricated and measured systematically in an in situ transmission electron microscope to perform a RESET/SET process under pulsed and dc voltage swept mode, respectively. During the switching, we observed the dynamic evolution of the phase transformation process. The switching behavior resulted from crystalline/amorphous change and revealed that a long pulse width would induce the amorphous or polycrystalline state by different pulse amplitudes, supporting the improvement of the writing speed, retention, and endurance of PCRAM.
Charge Quantity Influence on Resistance Switching Characteristic During Forming Process
(2013-04-01)
Chu, Tian-Jian
;
Chang, Ting-Chang
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Tsai, Tsung-Ming
;
Wu, Hsing-Hua
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Chen, Jung-Hui
In this letter, we presented that the charge quantity is the critical factor for forming process. Forming is a pivotal process in resistance random access memory to activate the resistance switching behavior. However, overforming would lead to device damage. In general, the overshoot current has been considered as a degradation reason during the forming process. In this letter, the quantity of charge through the switching layer has been proven as the key element in the formation of the conduction path. Ultrafast pulse forming can form a discontinuous conduction path to reduce the operation power.
On-Current Decrease After Erasing Operation in the Nonvolatile Memory Device With LDD Structure
(2011-08-01)
Chang, Geng-Wei
;
Chang, Ting-Chang
;
Syu, Yong-En
;
Tai, Ya-Hsiang
;
Jian, Fu-Yen
The on-current decrease phenomenon is observed after erasing operation in the silicon-oxide-nitride-oxide-silicon thin-film transistors (TFTs) with lightly doped drain (LDD) structure. As nonvolatile memory, when the TFT is programmed again, the on-current decrease phenomenon can be recovered. The on-current decrease and recovery are explained by the energy band diagrams at different drain biases. The explanation implies that this phenomenon only appears in the device with LDD structure, but not in the device without LDD structure, which is experimentally verified.
A Novel SONOS Memory With Recessed-Channel Poly-Si TFT via Excimer Laser Crystallization
(2012-04-01)
Lee, I-Che
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Tsai, Chun-Chien
;
Kuo, Hsu-Hang
;
Yang, Po-Yu
;
Wang, Chao-Lung
A silicon-oxide-nitride-oxide-silicon memory with recessed-channel (RC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) via excimer-laser crystallization (ELC) has been demonstrated to achieve a high mobility of similar to 400 cm(2)/V . s and a large ON/OFF current ratio of similar to 10(8). Such a high performance is because the RC poly-Si TFTs possess only one perpendicular grain boundary (GB) in the channel and the corresponding protrusion at this GB. In addition, the proposed devices also exhibited the largest memory window of 2.63 V in 10 ms with respect to 2.37 and 1.31 V for the conventional-ELC and solid-phase-crystallized ones, respectively. Since the silicon grain growth could be artificially controlled, the device-to-device uniformity could be significantly improved. Therefore, such a simple scheme is promising for applications of low-temperature poly-Si TFTs in 3-D ICs and system on panel.
Photoerasable Organic Nonvolatile Memory Devices Based on Hafnium Silicate Insulators
(2011-12-01)
Chen, Fang-Chung
;
Chang, Hsiao-Fen
;
光電工程學系
;
顯示科技研究所
;
Department of Photonics
We have prepared photoerasable organic nonvolatile memories using high-dielectric (high-k) hafnium silicate as device insulators. The high-k material can effectively lower the operating voltage of the organic memory devices. The nonvolatile memory can be written by applying a gate bias and be effectively erased by photon illumination. The spectral study of the photoinduced recovery effect indicated that the erasing mechanism should be relevant to the recombination between the trapped charges and the photogenerated exctions.

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