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The Impact of Layout Dependent Intrinsic Parasitic RLC on High Frequency Performance in 3T and 4T Multi-finger nMOSFETs
(2019-01-01)
Guo, Jyh-Chyurn
;
Ou, Jyun-Rong
;
Lin, Jinq-Min
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new observation of significant differences in the high frequency device parameters and performance like f(T) and f(MAX) is identified from the comparison of 3-terminal (3T) and 4-terminal (4T) multi-finger (MF) nMOSFETs. Through an extensive characterization on the intrinsic Z- and Y-parameters, it is found that the major impact comes from the particular increase of intrinsic parasitic resistances and inductances at the source terminal, namely R-s,R-int and L-s,L-int in the 4T MF MOSFETs. The proposed analytical models as a function of key device parameters incorporating the influence of the intrinsic parasitic RLC through high frequencies can accurately predict f(T) and f(MAX) degradation in 4T MF nMOSFETs as well as the complicated layout dependent effects. The experimental results and analytical models can be useful to facilitate MF devices layout optimization for high frequency design and performance improvement.
High Performance Metal-Gate/High-kappa GaN MOSFET With Good Reliability for Both Logic and Power Applications
(2016-09-01)
Yi, Shih-Han
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Ruan, Dun-Bao
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Di, Shaoyan
;
Liu, Xiaoyan
;
Wu, Yung Hsien
The gate-recessed GaN MOSFET on a Si substrate is demonstrated to achieve a record highest normalized transistor current (mu C-ox) of 335 mu A/V-2 (410 mA/mm at L-G = 5 mu m and only V-G = 4 V), I-ON/I-OFF of 9 orders of magnitude, small 79 mV/dec sub-threshold slope, a low oxide/GaN interface trap density of 1.2 x 10(10) eV(-1)/cm(2), a low on-resistance of 17.0 Omega-mm, a high breakdown voltage of 720-970 V, and excellent reliability of only 40 mV Delta V-T after 175 degrees C 1000 s stress at maximum drive current. Such excellent device integrities are due to the high-kappa gate dielectric and the high conduction band offset (Delta E-C) of SiO2/GaN. From the calculation results of self-consistent Schrodinger and Poisson equations, the good reliability of GaN MOSFET is related to the confined carrier density within the GaN channel, which is in sharp contrast to the strong wave-function penetration into the high-trap density AlGaN barrier in the AlGaN/GaN HEMT.
Very low noise in 90nm node RF MOSFETs using a new layout
(2007-01-01)
Kao, H. L.
;
Chin, Albert
;
Liao, C. C.
;
McAlister, S. P.
;
電子工程學系及電子研究所
We have directly measured a record low minimum noise figure (NFmin) of 0.46 dB at 10 GM, along with a high 16.6 dB Associated Gain, in an 8-finger 90 nm node MOSFET (L-G = 65nm) without de-embedding. At 18 GHz, NFmin was 0.83 dB with 13.5 dB gain. This was achieved using a microstrip line layout to screen the RF noise generated by the lossy substrate.
Impact of Highly Compressive Interlayer-Dielectric-SiNx Stressing Layer on 1/f Noise and Reliability of SiGe-Channel pMOSFETs
(2010-12-01)
Chen, Yu-Ting
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Chen, Kun-Ming
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Liao, Wen-Shiang
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Huang, Guo-Wei
;
Huang, Fon-Shan
The 1/f noise and reliability of SiGe-channel pMOSFETs with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx stressing layer have been studied in this letter. The SiGe-channel devices with a highly compressive CESL layer have higher drain current and lower 1/f noise than the conventional SiGe-channel and bulk-Si devices. However, the device reliability is degraded while integrating with the highly compressive CESL layer. By examining the effective oxide-trap densities under hot-carrier instability stress, we find that the incorporated hydrogen in gate oxide during CESL layer deposition may play an important role on the 1/f noise and device reliability.
High-Performance GaN MOSFET With High-k LaAlO3/SiO2 Gate Dielectric
(2012-01-01)
Tsai, C. Y.
;
Wu, T. L.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Using a high-k LaAlO3/SiO2 gate dielectric, the recessed-gate GaN MOSFET has a low threshold voltage (V-t) of 0.1 V, low on-resistance (R-on) of 13.5 Omega . mm, high breakdown voltage of 385 V, high transconductance (g(m)) of 136 mS/mm, and record-best normalized drive current (mu C-ox) of 172 mu A/V-2. Such excellent device integrity is due to the small capacitance equivalent thickness of 3.0 nm, using a high-k gate dielectric and recessed-gate etching.
PBTI Investigation of MoS2 n-MOSFET With Al2O3 Gate Dielectric
(2017-05-01)
Yuan, Hui-Wen
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Shen, Hui
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Li, Jun-Jie
;
Shao, Jinhai
;
Huang, Daming
For the first time, we report the positive bias temperature instability of the back gated multilayer MoS2 n-MOSFETs with Al2O3 gate dielectric. In the stress phase, the Id-Vg curve shifts to the positive gate bias. In the recovery phase, it shifts back to the negative gate bias. After 5000 s recovery, it completely recovers to that of the fresh device. The results indicate that the voltage shift is solely due to trapping and detrapping of the pre-existing border traps in the Al2O3 dielectric. The traps consist of fast and slow components with the capture time constants of 7 and 1.8 x 10(2) s and the emission time constants of 15 and 1.0 x 10(3) s, respectively. The results from first-order trapping and detrapping calculations are in overall agreements with 12 measured Delta Vg curves including six under stress voltages and six in the recovery phases. The energy densities for the fast and slow traps are derived to be in the order of 10(13) cm(- 2) eV(-1) above the bottom of the MoS2 conduction band.
Analysis of abnormal transconductance in body-tied partially-depleted silicon-on-insulator n-MOSFETs
(2017-12-31)
Lin, Chien-Yu
;
Chang, Ting-Chang
;
Liu, Kuan-Ju
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Chen, Li-Hui
;
Chen, Ching-En
This research investigates the mechanism of abnormal transconductance (Gm) and abnormal charge pumping current (I-CP) in body-tied partially-depleted silicon-on-insulator n-channel metal-oxide-semiconductor field effect transistors. The I-CP second hump region increases with channel length, yet is not affected by channel width. The cross-sectional view of the L-gate structure along the width direction demonstrates that a part of the poly gate area near the body contact is covered by a P+ implant, inducing a parasitic channel under the P+ poly gate. This parasitic channel leads to the abnormal Gm and I-CP hump, and such mechanism is further verified by body floating devices.
Investigation of Traps at MoS2/Al2O3 Interface in nMOSFETs by Low-Frequency Noise
(2016-04)
Yuan, Hui-Wen
;
Shen, Hui
;
Li, Jun-Jie
;
Shao, Jinhai
;
Huang, Daming
A new method is proposed to distinguish the contributions of the low-frequency noise (LFN) from the channel and the source/drain Schottky contacts in MOS devices. The method is applied to back-gated nMOSFETs with MoS2 channel and Al2O3 gate dielectric. To avoid a possible noise signal contamination from the top MoS2 surface by oxygen or water molecules absorption, the nMOSFETs with multilayer MoS2 are fabricated, and the measurements are carried out in the vacuum. The trap density Not at the MoS2/Al2O3 interface is derived for the first time using the proposed method. It is found that the Not responsible to LFN depends strongly on the surface potential, ranging from 4 x 10(10) cm(-2) in the weak over-drive region to 5 x 10(11) cm(-2) in the strong over-drive region.
Effects of In-Situ Plasma-Enhanced Atomic Layer Deposition Treatment on the Performance of HfO2/In0.53Ga0.47As Metal-Oxide-Semiconductor Field-Effect Transistors
(2016-08)
Quang Ho Luc
;
Cheng, Shou Po
;
Chang, Po Chun
;
Huy Binh Do
;
Chen, Jin Han
In-situ plasma-enhanced atomic layer deposition (PEALD) technique was employed for device passivation to realize a high-performance inversion-mode HfO2/In0.53Ga0.47As metal-oxide-semiconductor field-effect transistor (MOSFET). Excellent quality of gate dielectric is enabled by utilizing the PEALD-aluminum nitride as a pre-gate interfacial layer, followed by a post-gate remote-plasma gas treatment. In-situ PEALD treatment led to enhanced dc characteristics, such as drain current, peak transconductance, subthreshold swing, OFF leakage current, and effective electron mobility. X-ray photoelectron spectroscopy analysis indicates a reduction of In-and Ga-related signals. Furthermore, small drain current hysteresis and low-interface state density (D-it) value confirm a high interfacial quality for the high-k/III-V structure. Overall, the PEALD passivation for HfO2/In0.53Ga0.47As interface shows a remarkable improvement on the MOSFET performance.
Impact of Inner Pickup on ESD Robustness of Multifinger MOSFET in 28-nm High-k/Metal Gate CMOS Process
(2015-12-01)
Lin, Chun-Yu
;
Chang, Pin-Hsin
;
Chang, Rong-Kun
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The impact of pickup structure on electrostatic discharge (ESD) robustness of multifinger MOSFET in 28-nm high-k/metal gate CMOS process was investigated in this paper. Verified in silicon, the multifinger MOSFET without the pickup structure inserted into its source region can sustain the higher ESD level and more compact layout area.

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