學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Search Results

Now showing 1 - 10 of 13

Improved Charge Pump Design and Ex Vivo Experimental Validation of CMOS 256-Pixel Photovoltaic-Powered Subretinal Prosthetic Chip
(2020-05-01)
Kuo, Po-Han
;
Wong, Oi-Ying
;
Tzeng, Chi-Kuan
;
Wu, Pu-Wei
;
Chiao, Chuan-Chin
An improved design of CMOS 256-pixel photovoltaic-powered implantable chip for subretinal prostheses is presented. In the proposed subretinal chip, a high-efficiency fully-integrated 4x charge pump is designed and integrated with on-chip photovoltaic (PV) cells and a 256-pixel array with active pixel sensors (APS) for image light sensing, biphasic constant current stimulators, and electrodes. Thus the PV voltage generated by infrared (IR) light can be boosted to above 1V so that the charge injection is increased. The proposed chip adopts the 32-phase divisional power supply scheme (DPSS) to reduce the required supply current and thus the required area of the PV cells. The proposed chip is designed and fabricated in 180-nm CMOS image sensor (CIS) technology and post-processed with biocompatible IrOx electrodes and silicone packaging. From the electrical measurement results, the measured stimulation frequency is 28.3 Hz under the equivalent electrode impedance load. The measured maximum output stimulation current is 7.1 mu A and the amount of injected charges per pixel is 7.36 nC under image light intensity of 3200 lux and IR light intensity of 100 mW/cm(2). The function of the proposed chip has been further validated successfully with the ex vivo experimental results by recording the electrophysiological responses of retinal ganglion cells (RGCs) of retinas from retinal degeneration (rd1) mice with a multi-electrode array (MEA). The measured average threshold injected charge is about 3.97 nC which is consistent with that obtained from the patch clamp recording on retinas from wild type (C57BL/6) mice with a single electrode pair.
An Optically-Powered 432 MHz Wireless Tag for Batteryless Internet-of-Things Applications
(2019-09-01)
Cheng, Hao-Chung
;
Chen, Yen-Ting
;
Chen, Po-Hung
;
Liao, Yu-Te
;
電子工程學系及電子研究所
This paper presents an optically-powered wireless tag, integrating a charge pump (CP) and a low-power RF transmitter for batteryless Internet-of-Things (IoT) applications. The proposed charge pump with hysteresis regulation mechanism (HRM) powers the transmitter circuit using indoor light energy. The charge pump enables the transmitter whenever the output capacitor stores sufficient energy and guarantees a short period signal transmission. The proposed low-power transmitter contains the subharmonically injection-locked PLL and the capacitive coupling technique to achieve a large frequency multiplication ratio. The proposed batteryless wireless chip is fabricated in 0.18-mu m CMOS process. The measurement results demonstrate that the proposed charge pump provides a 1.1 to 1.3 V hysteresis regulated voltage under indoor light illumination larger than 300 lux. The charge pump achieves 84.1% peak efficiency and the communication distance of 3 meters is demonstrated while only consuming 248 mu W.
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process
(2019-09-01)
Luo, Zhicong
;
Yu, Li-Chin
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A wide-output, power-efficient, high-voltage charge pump with a variable number of stages is proposed and realized in a 0.18 mu m 1.8 V/3.3 V CMOS process. The proposed stage selection circuit changes the node voltages in the charge pump circuit in a domino effect to ensure that the maximum voltages across the terminals of each transistor are kept within the normal supply voltage (V-DD). The stage selection circuit is able to bypass or activate each stage of the charge pump. Experimental results indicate that the proposed charge pump provides a wide-output voltage range: 3.3-12.6 V from a 3.3 V input source. A peak efficiency of 70% was reached in the charge pump at a current loading of 3.5 mA. By selecting the optimal number of active stages, the overall power efficiencies can be greater than 60% under the output voltages of 4.8 V, 8.1 V, and 10.8 V, respectively. By optimizing the number of active stages, an increase of up to 35% power efficiency can be gained. The proposed stage selection circuit is applicable to other on-chip wide-output charge-pumps.
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS
(2019-05-01)
Liu, Chi-Wei
;
Chen, Yi-Lun
;
Liao, Pei-Chun
;
Lin, Shiau-Pin
;
Wang, Ting-Wei
This brief presents a high-efficiency battery management unit combining a single-inductor dual-output (SIDO) buck converter with two charge pumps (CPs) to provide three voltage levels (6 V, -6 V, and 2 V) for neuron stimulators in implantable medical devices. The stacked power stage in the buck converter mitigates the voltage stress issue in the power stage to manage 3.2-4.8 V battery voltage. By cascading a buck converter and CPs, the voltage across the CP power stage is reduced to generate 6 V and -6 V high voltage outputs without using high voltage devices. As a result, the proposed battery management could provide 6 V, -6 V, and 2 V output voltages from 3.2 to 4.8 V input voltage using a 180-nm standard CMOS process. The measurement results demonstrate that the proposed battery management achieved a peak efficiency of 82.9% with an available input voltage of 3.2-4.8 V.
A dual phase charge pump with compact size
(2007-01-01)
Hsieh, Chun-Yu
;
Fan, Po-Chin
;
Chen, Ke-Horng
;
交大名義發表
;
National Chiao Tung University
In this paper, the regulated dual phase charge pump with compact size is presented. This charge pump uses the dual phase technique to reduce the output ripple and proposes a new power stage to define the stability of the overall system. This charge pump provides output voltage 5V and maximum load current 50mA with the constant frequency regulation. This design is based on TSMC 0.35 mu m 3.3V/5V CMOS technology.
An 80% Effeciency and Highly Adaptable PV Energy Harvest Circuitry With MPPT for IOT Devices
(2017-01-01)
Cheng, Yuan-Po
;
Chao, Paul C. -P.
;
Men, Guan-Yu
;
Yang, Ching-Cheng
;
Wang, Tong-Wen
An on-chip DC-DC converter for energy harvesting is proposed for a new battery-less solar cell tag applied to the Internet of Things (IoTs) devices. The main purpose of this design is to maximize the transfer efficiency and to stably provide a high enough supply voltage to the back-end loads. The overall circuit consists of a cross-coupled charge pump, a maximum power point tracking (MPPT) circuit, a timing control circuit and regulator. The input voltage range is from 0.45V to 3V. The output voltage can be boosted to the required level, in the range of 1V to 3.3V, with more than 60% power conversion efficiency. The throughput power is at least 500 mu W. A gated clock frequency modulation circuit is designed and adopted in the MPPT unit to lock the input resistance of the charge pump. In addition, a low-dropout (LDO) regulator circuit is used to provide a stable voltage to the load. The experimental results of chip show that the maximum power conversion efficiency (PCE) is 80% at 33 mu W input power condition.
A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications
(2018-06-01)
Luo, Zhicong
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
;
Department of Electronics Engineering and Institute of Electronics
A high-voltage-tolerant and power-efficient stimulator with adaptive power supply is proposed and realized in a 0.18- mu m 1.8-V/3.3-V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent issues of electrical overstress and gate-oxide reliability in low-voltage transistors. The on-chip high-voltage generator uses a pulse-skip regulation scheme to generate a variable dc supply voltage for the stimulator by detecting the headroom voltage on the electrode sites. With a dc input voltage of 3.3 V, the onchip high-voltage generator provides an adjustable dc output voltage from 6.7 to 12.3 V at a step of 0.8 V, which results in a maximal system power efficiency of 56% at a 2400-mu A stimulus current. The charge mismatch of the stimulator is down to 1.7% in the whole stimulus current range of 200-3000 mu A. The in vivo experiments verified that epileptic seizures could be suppressed by the electrical stimulation provided by the proposed stimulator. In addition, the reliability measurements verified that the proposed stimulator is robust for electrical stimulation in medical applications.
Study of Front End of CMOS RFID Tag with Inductively-coupled Broadband Antenna
(2007)
Kao, Yao-Huang
;
Liu, Chia-Chuan
;
Kuo, Hung-Chang
;
電信工程研究所
;
Institute of Communications Engineering
Radio frequency identification (RFID) has received much attention. The ac to dc conversion efficiency is crucial for long range application in UHF band. The front end of the passive tag combined with the broadband antenna at 915MHz is investigated. Two subjects of high efficient charge-pump and antenna matching are focused. The chip is fabricated by TSMC 0.18um 1P6M CMOS. The antenna is on the 0.4mm FR4 pc board. With ten stages of capacitor-diode pair, the multiplier factor is 8.575 and dc voltage can reach to 3.4V and is regulated to 850mV with input power lies between 6 similar to 8dBm. Under matching, the communication range can reach to 4m.
A Fully-Integrated Charge Pump for Self-Powered Implantable Retinal Prostheses
(2016)
Wong, Oi-Ying
;
Chen, Po-Hung
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
This paper presents a compact fully-integrated charge pump based voltage doubler for self-powered implantable retinal prostheses. The target input voltage is 0.55 V to meet the output voltage of on-chip photovoltaic cells, and the target output is around 1 V to provide sufficient current for neuron stimulation. Several techniques are adopted in the proposed design, including gate-boosting circuits to enhance current driving capability, a time-interleaving technique to reduce the size of the output capacitor, and a non-overlapping clock generator to suppress the shoot-through current. The proposed charge pump was implemented in 0.18 mu m CMOS process with core chip area of 700 mu m x 280 mu m. The measurement results demonstrate that the proposed charge pump is capable of providing around 1 V output from an input voltage of 0.55 V with 500 mu A loading current. The peak power efficiency is 73.4 % and the total area is 700 mu m x 280 mu m.
High efficiency MOS charge pumps based on exponential-gain structure with pumping gain increase circuits
(2006-05-01)
Chang, LK
;
Hu, CH
;
電控工程研究所
;
Institute of Electrical and Control Engineering
Novel MOS charge pumps utilizing an exponential-gain structure and pumping gain increase (PGI) circuits with high voltage transfer efficiency to generate boosted output voltages are described. By using the PGI circuits, the threshold voltage problem of the MOSFET used as a switch is solved, and the limitation of the diode-configured output stage is removed. Thus, the boosted output voltage increases linearly as compared to the pumping stage number. An exponential-gain structure is also presented as a further application of the PGI circuit. By using this structure, fewer voltage pump stages are needed to obtain the required output voltage. For 1.5-V supply voltage operation, a four-time series (1.5 V-to-6 V) is demonstrated using the new techniques. Simulation and experimental results have shown that this design has good efficiency with a low-input supply voltage such as a one battery cell.

學術出版;;Publications

Browse

Filters

Settings

Sort By

Results per page

🏛️國立陽明交通大學機構典藏

Search Results