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Statistical Prediction of Nanosized-Metal-Grain-Induced Threshold-Voltage Variability for 3D Vertically Stacked Silicon Gate-All-Around Nanowiren-MOSFETs
(1970-01-01)
Sung, Wen-Li
;
Li, Yiming
;
交大名義發表
;
電機工程學系
;
電信工程研究所
In this study, we present a statistically accurate model to predict the threshold-voltage variability (sigma V-th) efficiently for three-dimensional (3D) vertically stacked silicon (Si) gate-all-around (GAA) nanowire (NW)n-MOSFETs with multi-channels. The statistical results indicate that the sigma V(th)decreases exponentially by increasing metal grain number (MGN), which is unitless. Additionally, the magnitude of sigma V(th)was calculated for various MGNs, which joins the normality test with Anderson-Darling test. Therefore, the model with MGN can be implemented by nonlinear regression with a regression coefficient of approximately one. From this model and the perspective of process, more 3D vertically stacked channels can reduce the value and sensitivity of sigma V-th. This study provides useful information from statistics to explain the experiment results for 3D vertically stacked Si GAA NWn-MOSFETs with multi-channels.
Dewetting of Swollen Poly(3-hexylthiophene) Films during Spin-Coating Processes: Implications for Device Fabrication
(2018-05-01)
Chung, Pei-Yun
;
Cheng, Ming-Hsiang
;
Tseng, Hsiao-Fan
;
Liu, Chih-Ting
;
Chiu, Tang-Yao
Poly(3-hexylthiophene) (P3HT) films have been usually prepared by spin-coating for the applications of electronic devices such as organic photovoltaic devices (OPV) and organic field-effect transistors (OFETs). The wetting and dewetting behaviors of the swollen P3HT films during the spin-coating processes, however, are still poorly understood. In this work, we investigate the dewetting behaviors of P3HT thin films and the formation of ring structures during the spin-coating process by controlling the spin rates and the solution temperatures. Quantitative studies of the dewetting phenomena are conducted by measuring the sizes of the ring structures of the dewetting patterns. It is observed that the sizes of the ring structures are larger at lower spin rates because of the longer dewetting times allowed during the spin-coating processes. More importantly, the dewetting behaviors of the P3HT films are discovered to be affected by the formation of the P3HT nanowhiskers (nanowires). This work offers a deeper understanding of the dewetting behaviors of swollen P3HT films during the spin-coating processes, which is crucial for the development of P3HT-based optoelectronic devices.
Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process
(2019-11-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of $5.3\times9$ nm(2) and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit a remarkable I-on-I-off ratio of more than 10(8). We demonstrated stacked channels, double layers, GAA NC-FET with a threshold voltage ( ${V}_{\textit {TH}}$ ) of 0.61 V, and a superior subthreshold behavior with an average and minimum sub- ${V}_{\textit {TH}}$ slope of 43.85 and 26.84 mV/dec, respectively. An additional ZrO2 seed layer was inserted under the Hf $_{{1-}{x}}$ ZrxO2 layer to improve ferroelectric crystallinity. Thus, the conventional crystallization annealing step can be omitted due to the presence of the orthorhombic phase ( ${o}$ -phase) before further post-metal annealing (PMA).
Plasmonic Nanolasers Enhanced by Hybrid Graphene-Insulator-Metal Structures
(2019-08-01)
Li, Heng
;
Li, Jhu-Hong
;
Hong, Kuo-Bin
;
Yu, Min-Wen
;
Chun, Yi-Cheng
Graphene is a two-dimensional (2D) structure that creates a linear relationship between energy and momentum that not only forms massless Dirac fermions with extremely high group velocity but also exhibits a broadband transmission from 300 to 2500 nm that can be applied to many optoelectronic applications, such as solar cells, light-emitting devices, touchscreens, ultrafast photodetectors, and lasers. Although the plasmonic resonance of graphene occurs in the terahertz band, graphene can be combined with a noble metal to provide a versatile platform for supporting surface plasmon waves. In this study, we propose a hybrid graphene-insulator-metal (GIM) structure that can modulate the surface plasmon polariton (SPP) dispersion characteristics and thus influence the performance of plasmonic nanolasers. Compared with values obtained when graphene is not used on an Al template, the propagation length of SPP waves can be increased 2-fold, and the threshold of nanolasers is reduced by 50% when graphene is incorporated on the template. The GIM structure can be further applied in the future to realize electrical control or electrical injection of plasmonic devices through graphene.
Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits
(2019-05-01)
Li, Yiming
;
Chen, Chieh-Yang
;
Chuang, Min-Hui
;
Chao, Pei-Jung
;
電機工程學系
In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal-oxide-semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device's nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device-circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation.
The fabrication and application of Ni-DNA nanowire-based nanoelectronic devices
(2019-06-01)
Chang, Pang-Chia
;
Chang, Chia-Yu
;
Jian, Wen-Bin
;
Yuan, Chiun-Jye
;
Chen, Yu-Chang
DNA is a self-assembled, double stranded natural molecule that can chelate and align nickel ions between its base pairs. The fabrication of a DNA-guided nickel ion chain (Ni-DNA) device was successful, as indicated by the conducting currents exhibiting a Ni ion redox reaction-driven negative differential resistance effect, a property unique to mem-elements (1). The redox state of nickel ions in the Ni-DNA device is programmable by applying an external bias with different polarities and writing times (2). The multiple states of Ni-DNA-based memristive and memcapacitive systems were characterized (3). As such, the development of Ni-DNA nanowire device-based circuits in the near future is proposed.
High Q/V-m hybrid photonic-plasmonic crystal nanowire cavity at telecommunication wavelengths
(2015-01-01)
Chiang, Chih-Kai
;
Chung, Yi-Cheng
;
Cheng, Pi-Ju
;
Wu, Chien-Wei
;
Chang, Shu-Wei
We haw analyzed a hybrid photonic-plasmonic crystal nanocavity consisting of a silicon grating nanowire adjacent to a metal surface with a gain gap between. The hybrid plasmonic cavity modes are highly confined in the gap due to the coupling of photonic crystal cavity modes and surface plasmonic gap modes. Using the finite-element method, we numerically solve guided modes of the hybrid plasmonic waveguide at a wavelength of 1.55 jim. The modal characteristics such as wave guide confinement factors and modal losses of the fundamental hybrid plasmonic modes are explored as a function of the groove depth at various gap heights. After that, we show the band structure of the hybrid crystal modes, corresponding to a wide band gap of 17.8 THz. To effectively trap the optical modes, we introduce a single defect into the hybrid crystal. At a deep sub-wavelength defect length as small as 180 nm, the resonant mode exhibits a high quality factor of 566.5 and an ultrasmall mode volume of 0.00186 (ln)3 at the resonance wavelength of 1.55 gm. In comparison to the conventional photonic crystal nanowire cavity in the absence of metal surface, the figure of merit QIVm is enormously enhanced around 15 times. The proposed nanocavities open up the opportunities for various applications with strong light-matter interaction such as nanolasers and bio sensors.
The growth of pine-leaf-like hierarchical SnO2 nanostructures
(2014-01-01)
Dee, Chang Fu
;
Tiong, Teck Yaw
;
Varghese, Binni
;
Sow, Chorng-Haur
;
Wong, Yuan-Yee
Pine-leaf-like SnO2 hierarchical nanostructures (NSs) were grown by a two-step vapour transport deposition process with a combination of vapour-solid and vapour-liquid-solid mechanisms at the primary and secondary processes, respectively. This type of hierarchical structure consisted of SnO2 trunk with homo-branching nanowires (NWs). The branched NWs connected the trunk NWs at included angles of 56 degrees and 90 degrees for two different types of hierarchical NSs. Based on the thermodynamic calculation, the formation of branched NWs at those angles are all energetically favourable.
Comprehensive Study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory With an HfO2 Charge Trapping Layer
(2011-03-01)
Chen, Lun-Jyun
;
Wu, Yung-Chun
;
Chiang, Ji-Hong
;
Hung, Min-Feng
;
Chang, Chin-Wei
This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO2 charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 mu s. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pigate NWs poly-Si TFT NVM with a Si3N4 charge-trapping layer was also fabricated. Since HfO2 has a deeper conduction band than Si3N4, the device with the HfO2 charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si3N4 charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO2 charge-trapping layer to undergo more P/E cycles than that with the Si3N4 charge-trapping layer.
Timing and Power Fluctuations on Gate-All-Around Nanowire CMOS Circuit Induced by Various Sources of Random Discrete Dopants
(2017-01-01)
Sung, Wen-Li
;
Chao, Pei-Jung
;
Li, Yiming
;
分子醫學與生物工程研究所
;
電信工程研究所
Random dopant fluctuation (RDF) is one of fluctuation sources in sub-7-nm semiconductor technology node. In this paper, we estimate the timing and power fluctuations on 10-nm-gate gate-all-around (GAA) silicon nanowire (NW) complementary metal-oxide-semiconductor (CMOS) circuit induced by various random discrete dopants (RDDs) from channel (with/without doping), source/drain (S/D) extensions and penetration from S/D extensions. The 3D quantum mechanical transport and non-equilibrium Green's function (NEGF) models were used for the NW CMOS circuit. The experimentally validated device simulation indicates that at a similar threshold voltage, CMOS devices without channel doping possess 49.5% reduction on the normalized fluctuation of the static power consumption due to the reduction of sigma V-th and sigma I-off. The normalized fluctuation of dynamic power is comparable with/without channel doping due to small variation of the gate capacitance. Because of reduction of sigma I-sat, the normalized fluctuation of short-circuit power of CMOS circuit was reduced from 21.7% to 10.2% without channel doping. And, we found that the uctuations of the timing, noise margin (NM) and power consumption of the NW CMOS circuit follow the trend of sigma V-th. From the point of view of N-/P-type NW MOSFETs caused by RDF, this study may show the fluctuation of CMOS circuit performance highly influenced by the key parameters of N-/P-type NW MOSFETs.

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