前瞻矽奈米元件變異性及傳輸特性綜合研究(II)
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在此研究計畫中，我們將對以矽為基底的前瞻奈米元件，針對其變異性及載子傳輸
特性進行綜合研究。在工作項目一中，我們將分別對超薄基體(ultra-thin-body)，多
閘極(multi-gate)以及環閘極(gate-all-around)金氧半場效電晶體，建立一套包含
Poisson 及Schrodinger 方程式之解的理論架構。利用這一套可考慮量子侷限效應的解
析解模型，我們將研究這三種元件結構對製程變異的敏感度。我們的元件模型也將有
助於未來奈米級元件的設計。在工作項目二中，我們將廣泛地研究奈米CMOS 場效電晶
體的隨機不匹配特性。這項研究不僅對使用先進CMOS 元件的電路設計很重要，也有助
於對奈米元件的本質參數變異(intrinsic parameter fluctuation)的根本了解。在工
作項目三中，我們將對奈米CMOS 的戴子傳輸特性進行研究。這項研究將有助於了解極
微縮奈米元件的戴子傳輸機制，也對未來提昇戴子遷移率的元件設計有所幫助。
In this project we conduct a comprehensive study of variability and carrier transport for nano-CMOS. In task I, we will establish a theoretical framework that includes the solutions of Poisson and Schrödinger equations for ultra-thin-body, multi-gate and gate-all-around MOSFETs. Using the analytical models, we will assess the sensitivity of these structures to process variations considering quantum-confinement effects. Our physical models will be instrumental for future nanoscale device designs. In task II, we will conduct a comprehensive study of random mismatch for nano-CMOS. This study is important not only for circuit designs using advanced CMOS devices, but also for the fundamental understanding of intrinsic parameter fluctuations in ultra-scaled devices. In task III, we will conduct a comprehensive study of carrier transport for nano-CMOS. Our investigation will contribute to unveiling several puzzles regarding carrier transport in ultra-scaled devices, as well as providing insights for future mobility scaling.
In this project we conduct a comprehensive study of variability and carrier transport for nano-CMOS. In task I, we will establish a theoretical framework that includes the solutions of Poisson and Schrödinger equations for ultra-thin-body, multi-gate and gate-all-around MOSFETs. Using the analytical models, we will assess the sensitivity of these structures to process variations considering quantum-confinement effects. Our physical models will be instrumental for future nanoscale device designs. In task II, we will conduct a comprehensive study of random mismatch for nano-CMOS. This study is important not only for circuit designs using advanced CMOS devices, but also for the fundamental understanding of intrinsic parameter fluctuations in ultra-scaled devices. In task III, we will conduct a comprehensive study of carrier transport for nano-CMOS. Our investigation will contribute to unveiling several puzzles regarding carrier transport in ultra-scaled devices, as well as providing insights for future mobility scaling.