標題: 前瞻性銻化物異質材料場效電晶體及其高速低功率元件與可調式高頻電路應用之研究---子計畫五:高速與低耗能邏輯應用之銻化物N及P通道異質接面場效電晶體
Antimony-Based N/P-Channel Heterojunction Field Effect Transistor for High-Speed and Low-Power Consumption Applications
作者: 張翼
CHANG EDWARD YI
國立交通大學材料科學與工程學系(所)
關鍵字: 銻化物;高速量子元件;電流截止頻率;低功率;邏輯特性;N型與P型通道
公開日期: 2010
摘要: 無線通訊的快速發展以及在矽半導體工業上面臨通道特性之物理極限,近年來III-V 族高速電晶體被視為明日之星應用於高速邏輯元件或是次毫米波段,而尋找更高速的載 子遷移率材料與新穎元件結構是科學家急於開發的目標,銦化銻材料為目前具有最高速 的電子移動率與飽和速度,更進一步由於在磊晶製程中可以施加應力等方式提高電洞遷 移率,所以銻化物半導體極具潛力開發N型與P型通道元件,達成互補式電晶體,應用於 高速低電壓類比與數位電路設計上。 本子計畫主要目的是製作高性能次奈米級銻化物之互補式N型與P型通道高速量子 元件,將使用不同閘極線寬(30 nm、40 nm、50 nm與80 nm),通道材料分別將使用InAsSb (N型通道)與InGaSb (P型通道),所製造的N-型元件與P-型元件截止頻率預計分別高於 550 GHz及200 GHz。評估其操作在超高頻率時,應用於超低消耗功率、高速邏輯電晶體 之可行性,此外此銻化物元件在較低電壓下操作,將可以大幅降低電晶體的消耗功率, 達到超低電壓、超低功率的操作需求,因應全球節能趨勢,發展綠色電子。並配合子計 畫(一)完成磊晶結構最佳化,並與子計畫(三)(四)共同合作建立高頻電路模型及基板材料 參數電性萃取與驗證,提供電性與子計畫(二)開發銻化物混合電路設計,最後整合總計 畫完成相位陣列收發機模組之實現。
The progress of wireless communication technologies are development rapidly. Meanwhile, the Si-industries are coming to an end beyond 22-nm node due to the mobility limit. As a result, III-V devices are the high potential transistor for high-speed and sub-millimeter wave applications. Searching high-carrier-mobility material and novel device architectures are main objectives for the engineers and researchers. The indium antimonide materials possess the highest electron mobility and saturation velocity. In addition, the hole mobility can be improved using the strain techniques in the progress of epitaxy. Therefore, Sb-based semiconductor shows great potential in fabrication of n/p-channel complementary circuit device for high-speed low-voltage analogy and digital applications. The main objective of this sub-program is to fabricate high performance Sb-based complementary n/p-channel QWFETs with over (fT) 550 GHz and 200 GHz, separately, using different gate lengths ranging from 30 – 80 nm, InAsSb and InGaSb for low-power consumption applications. Hence, the power consumption can be reduced effectively using Sb-based channel devices. The device epitaxial structure will be optimization with the sub-project (1). Additionally, the high-frequency circuit modelings are also built up from sub-project (3) and (4) and providing the information for sub-project (2). Finally, all the sub-projects will be integrated to realize the key components and circuit of the phase array module.
官方說明文件#: NSC99-2221-E009-164-MY3
URI: http://hdl.handle.net/11536/100488
https://www.grb.gov.tw/search/planDetail?id=2121913&docId=339748
Appears in Collections:Research Plans