奈米CMOS元件不均勻、雜和氧化層缺陷導致臨限電壓變異之研究(I)

Abstract

CMOS 元件通道長度的微小化，趨動電流的提升、閘極氧化層漏電流，可分別運用應力技術 (strained technique)、high-k 加上metal gate 來克服。唯獨短通道效應或通道掺雜引起的臨限 電壓變異性(Vth Variability)目前尚未能夠良好的解決，它源自於通道中的掺雜(dopant)，在面 積很小的情況下，其密度的多寡與分佈的不均勻(nonuniform)會影響到Vth，此效應稱之為 Random Dopant Fluctuation(RDF)。RDF 對Vth Variation 的影響會隨著製程條件與元件結構的 不同而有所改變。我們延續過去在CMOS 元件應力技術的研究成果，以及發展的各種可靠 性量測法，來研究RDF 及另一新穎的效應：稱之為Random Trap Fluctuation(RTF)，以了解 更小元件改進RDF 及RTF 的有效CMOS 元件設計方式。計劃目的有四：其一是探討次奈米 世代CMOS 元件RDF(Random Dopant Fluctuation)導致的Vth Variation 與元件結構製程參數 相關性。其二是利用電流雜訊量測法（ID-RTN），探討各種strained-Si 元件，Hot carrier stress 效應下，RTF(Random Trap Fluctuation)導致的Vth Variation 及可靠性的關聯性。其三是，利 用傳輸理論，了解RDF 及RTF 對趨動電流的影響，最後，將它應用於FinFET 結構的研究， 且以SRAM 為Test Vehicle 來驗證此一Vth variation 的改進方法。 本計劃為期三年。第一年目標是運用園區廠商先進的 28nm 製程研製bulk control CMOS 元 件和strained Si -SiGe/SiC CMOS 等先進元件，建立Takeuchi plot 與元件各製程參數的相關 性，進行RDF(Random Dopant Fluctuation)導致的Vth Variation 的研究。接著探討可靠性行 為，利用吾人在2009VLSI 發展的電流雜訊量測法（ID-RTN），探討bulk control CMOS 元 件RTF(Random Trap Fluctuation)導致的Vth Variation 及可靠性的關聯性。 第二年計劃，是探討strained-Si CMOS 元件中，strain 造成的Vth variation。其次，運用電流 雜訊量測法（ID-RTN），探討Random Trap Fluctuation 導致的 variation、以及運用傳輸理論， 探討Vth variation 和driving current 間的關聯性。以了解strained CMOS 元件在趨動電流、可 靠性及導致Vth Variation 的設計準則。 第三年計劃，我們將研究 Vth variation 對FinFET 元件的影響。透過利用FinFET 結構降低 channel impurity 可以有效改善Vth variation 並維持良好的短通道效應，這都有待驗證。探討 主題包括FinFET 元件的Vth variation，RTN 的研究、以及FinFET 傳輸特性等，探討何種 製程參數及設計有較佳的抑制Vth variation 能力。最後將以SRAM cell 做為Test vehicle 來 驗證此一結構用於提昇雜訊邊限(noise margin)的能力。 總之，本計畫的進行，將發展一系列的研究方法，配合更小尺寸 28nm 元件的製作，探討 Bulk-CMOS、strained-Si CMOS、及FinFET CMOS 三種不同元件，Random Dopant Fluctuation 及Random Trap Fluctuation 造成Vth variation 的影響和driving current 間的關聯性，及利於發 展未來更小尺寸CMOS 元件的製程及元件設計，除了學術研究外，這對於產業應用，有立 即的幫助。

With the further scaling of CMOS devices, the driving current enhancement and gate leakage reduction can be improved by the strained technique and high-k respectively. However, only the threshold voltage (Vth) variability can not be well controlled. It comes from the channel doping with its non-uniform distribution in a small area, which is called RDF(random dopant fluctuation). Vth variation also depends on the process conditions and device structure. In lieu of our experiences on the strained device technology and the associated reliability study, we will propose a new phenomenon which is called RTF(Random Trap Fluctuation) and will extend our study to both RDF and RTF induced Vth variations. Therefore, the purpose of this project are four folds, first is to study the RDF induced Vth variations and its dependence on the process and device design parameters, the second one is by using the RTN(Random Telegraph Noise) technique that we developed to study the RTF induced Vth variations for devices after the hot carrier stress. And, the third one is, based on the transport theory, to find the correlations between RDF/RTF and the device driving current. Finally, the above studies will be applied toward an improved design of FinFET devices with a well controlled Vth variation and demonstrate an SRAM cell to test its capability in the improvement of noise margin. This project includes 3 phases. In the first year, the goal is to fabricate a series of bulk-CMOS and strained CMOS devices using 28nm node technology of a cooperated foundry R&D, for experimental study. Then, we will setup the Takeuchi plot first based on the bulk-CMOS devices. Followed by a study on the RDF induced Vth variations and the dependences on the process and device parameters. Furthermore, by employing the RTN technique, experiments will be carried out for RTF induced Vth variations caused by the hot carrier stress. In the second year, the RDF induced Vth variations will be performed for strained CMOS devices. Then, by the RTN technique, RTF induced Vth variations will be examined. Also, the correlation between the Vth variation and the driving current will be studied. A device design guideline will be setup for the correlation between driving current, reliability, and Vth variation. In the final step of the year, a FinFET with better dopant control will be designed and fabricated. In the third year, first we will study the Vth variation in FinFET from the fabricated FinFET device in the latter half of the second year. The efficiency of the Vth variation through a good control of the dopant needs to be verified. The subjects which will be studied include: RDF induced Vth variation, RTF induced Vth variation, variation of transport parameters by the RDF and RTF induced variations and the correlation to the device driving current. Finally, the noise margin of an SRAM design as a test vehicle will be demonstrated. As a whole, this three-year proposal has been dedicated on developing an understanding of the RDF and RTF induced variations for the bulk, strained, and FinFET structure CMOS. It is intended to find a better solution for suppressing the Vth variation while keep a good driving current, good reliability design of various types of CMOS devices. These results will be expected to be useful for developing next generation CMOS technologies with a good control of RDF and RTF.