應用於多視角立體視訊之多核心節能智慧超微型通訊系統研究---子計畫二：以記憶儲存為重心之晶內資料傳輸應用於節能效益之多核心系統(I)

Abstract

隨著多核心系統的發展，系統晶片運算能力也隨之快速成長。然而晶片內資料傳 遞及資料儲存卻無法跟上多核心的發展腳步，進而成為多核心系統的瓶頸。因此，晶 片上不僅需要放置更多、更快、且低功耗的記憶體來提供儲存資料，也必須針對不同 的系統應用來建構相對應的資料傳輸平台及記憶體管理單元；為此，我們將提出一個 以記憶儲存為中心之晶內資料傳輸平台。此晶內資料傳輸平台將藉由階層式記憶體管 理單元及功率控管單元的協助與管理，提供異質多核心系統具節能效益之資料傳輸及 資料儲存，已達到系統效能的最佳化。此外，我們也將結合子計畫一共同建立跨階層 多核心系統分析模型，可針對特定應用提供一套系統性設計方法。本計劃所提出的晶 內資料傳輸平台專司晶內資料傳遞、資料儲存及其通訊協定之設計。我們將結合電路 與架構的設計，提出管理晶片上動態記憶體分配、頻寬、與資料傳輸之機制，此外還 負責管理晶片內外間資料傳輸之方法，且著重於低功耗之設計以解決多核心系統資料 傳遞及資料同步所將遇到之瓶頸。另外，為了更有效率地管理功耗，我們將設計新的 功率管理單元，並且使之與晶內傳輸平台相整合。在異質多核心架構方面，我們也將 針對總計劃所提出的超微型通訊系統，設計合適的串流處理器來加速超微型通訊系統 的資料運算。 在三年的計畫當中，我們將在第一年度研發階層式記憶體管理單元及低功率晶內 資料傳輸平台的架構建立。此外我們也將建立串流處理器的雛形。第二年度則完成記 憶體管理單元與晶內資料傳輸平台之溝通，並建立資料儲存及資料傳輸模型以完成跨 階層系統性分析方法，達到多核心系統之最佳化。另外在晶內資料傳輸平台上，我們 將導入功率控管單元以及偵錯除錯機制。第三年則參酌其他子計畫的規格來完成最後 晶內資料傳輸平台最終的細部架構，並且結合其他子計畫完成此節能效益之多核心系 統。

In modern SoC (system-on-chip) designs, computing capability is rapidly increasing with the development of multi-core systems. However, on-chip data communication and memory bandwidth grow slowly and become the performance bottleneck of multi-core systems. Therefore, large amounts of high speed and low power memories are indispensable to store a lot of computing data for multi-core systems. In view of this, we will propose a memory-centric on-chip data communication platform for energy-efficient multi-core systems. This platform will provide energy-efficient data communication and data storage to optimize performance of heterogeneous multi-core systems with a hierarchy memory management unit and a power management unit. The proposed memory-centric on-chip data communication platform will focus on data transfer, data storage and transmission control protocols. With circuit and architecture co-designs, we will propose dynamic scheduling mechanisms for memory allocation, bandwidth, and on-chip data communication. In order to have optimal power control, we will provide a novel power management unit and integrate it with the on-chip data communication platform. Nevertheless, in a heterogeneous multi-core architecture, we will design a specific stream processor to accelerate computations in a fentocell communication system. In first year, we will develop a hierarchy memory management unit and establish a low power on-chip data communication platform. Additionally, we also establish a prototype of the specific stream processor. In the second year, we will integrate the hierarchy memory management unit and on-chip data communication platform. Moreover, a power management unit and error correction mechanism will be included. We will also establish a memory model and a communication model to complete the cross-layer systematic design methodology, which will optimize multi-core system performance. In the third year, we will reference protocols of other sub-projects to complete the final detailed structure of memory-centric on-chip data communication platform. Additionally, we will complete the energy-efficient multi-core systems with other sub-projects.